From patchwork Tue Jun 30 22:09:55 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 33167 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5UMJlBM023740 for ; Tue, 30 Jun 2009 22:19:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754207AbZF3WTh (ORCPT ); Tue, 30 Jun 2009 18:19:37 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754025AbZF3WTh (ORCPT ); Tue, 30 Jun 2009 18:19:37 -0400 Received: from sg2ehsobe005.messaging.microsoft.com ([207.46.51.79]:47817 "EHLO SG2EHSOBE005.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753858AbZF3WTg (ORCPT ); Tue, 30 Jun 2009 18:19:36 -0400 Received: from mail54-sin-R.bigfish.com (10.210.100.250) by SG2EHSOBE005.bigfish.com (10.210.112.25) with Microsoft SMTP Server id 8.1.340.0; Tue, 30 Jun 2009 22:19:39 +0000 Received: from mail54-sin (localhost.localdomain [127.0.0.1]) by mail54-sin-R.bigfish.com (Postfix) with ESMTP id ECB7715E8167; Tue, 30 Jun 2009 22:19:35 +0000 (UTC) X-SpamScore: 1 X-BigFish: VPS1(zzzz1202hzzz32i65h) X-Spam-TCS-SCL: 4:0 Received: by mail54-sin (MessageSwitch) id 1246400374553816_23556; Tue, 30 Jun 2009 22:19:34 +0000 (UCT) Received: from ausb3extmailp02.amd.com (ausb3extmailp02.amd.com [163.181.251.22]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail54-sin.bigfish.com (Postfix) with ESMTP id D50D5F50051; Tue, 30 Jun 2009 22:19:33 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n5UMJU44011455; Tue, 30 Jun 2009 17:19:33 -0500 X-WSS-ID: 0KM2OO6-02-KQI-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 20AAC16A03DC; Tue, 30 Jun 2009 17:19:17 -0500 (CDT) Received: from SAUSEXMB3.amd.com ([163.181.22.202]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jun 2009 17:19:29 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by SAUSEXMB3.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jun 2009 17:19:29 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 00:09:54 +0200 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] fix AMD Fam10h unhandled MSRs Date: Wed, 1 Jul 2009 00:09:55 +0200 Message-ID: <1246399795-2606-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 X-OriginalArrivalTime: 30 Jun 2009 22:09:54.0758 (UTC) FILETIME=[7F640E60:01C9F9CF] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Linux wants to enable I/O port access to the PCI extended config space and thus writes a 1 into an AMD Fam10h MSR. Since we don't handle extended config space (yet?), we simply ignore this write (and return 0 on reads). Windows on the other hands checks whether the BIOS has setup MMI/O for config space accesses, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index af53f64..0c4f43e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -932,6 +932,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " "0x%x data 0x%llx\n", msr, data); break; + case MSR_FAM10H_MMIO_CONF_BASE: + if (data != 0) { + pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " + "0x%x data 0x%llx\n", msr, data); + return 1; + } + break; + case MSR_AMD64_NB_CFG: + break; default: if (!ignore_msrs) { pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", @@ -1049,6 +1058,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) case MSR_P6_EVNTSEL1: case MSR_K7_EVNTSEL0: case MSR_K8_INT_PENDING_MSG: + case MSR_AMD64_NB_CFG: + case MSR_FAM10H_MMIO_CONF_BASE: data = 0; break; case MSR_MTRRcap: