From patchwork Tue Mar 2 05:40:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 83122 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o225efra029997 for ; Tue, 2 Mar 2010 05:40:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751201Ab0CBFkb (ORCPT ); Tue, 2 Mar 2010 00:40:31 -0500 Received: from mga03.intel.com ([143.182.124.21]:19108 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750987Ab0CBFka (ORCPT ); Tue, 2 Mar 2010 00:40:30 -0500 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 01 Mar 2010 21:40:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.49,564,1262592000"; d="scan'208";a="249679290" Received: from yhuang-dev.sh.intel.com (HELO [10.239.13.129]) ([10.239.13.129]) by azsmga001.ch.intel.com with ESMTP; 01 Mar 2010 21:40:14 -0800 Subject: [PATCH -v2] Add savevm/loadvm support for MCE From: Huang Ying To: Avi Kivity , Anthony Liguori , Jan Kiszka Cc: Andi Kleen , "kvm@vger.kernel.org" Date: Tue, 02 Mar 2010 13:40:13 +0800 Message-ID: <1267508413.1640.88.camel@yhuang-dev.sh.intel.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Mar 2010 05:40:42 +0000 (UTC) --- a/qemu-kvm-x86.c +++ b/qemu-kvm-x86.c @@ -979,11 +979,33 @@ void kvm_arch_load_regs(CPUState *env, i set_msr_entry(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr); set_msr_entry(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); } +#ifdef KVM_CAP_MCE + if (env->mcg_cap && level == KVM_PUT_RESET_STATE) { + /* + * MCG_STATUS should reset to 0 after reset, while other MCE + * registers should be unchanged + */ + set_msr_entry(&msrs[n++], MSR_MCG_STATUS, 0); + } +#endif rc = kvm_set_msrs(env, msrs, n); if (rc == -1) perror("kvm_set_msrs FAILED"); +#ifdef KVM_CAP_MCE + if (env->mcg_cap && level == KVM_PUT_FULL_STATE) { + n = 0; + set_msr_entry(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); + set_msr_entry(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); + for (i = 0; i < (env->mcg_cap & 0xff); i++) + set_msr_entry(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); + rc = kvm_set_msrs(env, msrs, n); + if (rc == -1) + perror("kvm_set_msrs FAILED"); + } +#endif + if (level >= KVM_PUT_RESET_STATE) { kvm_arch_load_mpstate(env); kvm_load_lapic(env); @@ -1155,6 +1177,27 @@ void kvm_arch_save_regs(CPUState *env) return; } } + +#ifdef KVM_CAP_MCE + if (env->mcg_cap) { + msrs[0].index = MSR_MCG_STATUS; + msrs[1].index = MSR_MCG_CTL; + n = (env->mcg_cap & 0xff) * 4; + for (i = 0; i < n; i++) + msrs[2 + i].index = MSR_MC0_CTL + i; + + rc = kvm_get_msrs(env, msrs, n + 2); + if (rc == -1) + perror("kvm_get_msrs FAILED"); + else { + env->mcg_status = msrs[0].data; + env->mcg_ctl = msrs[1].data; + for (i = 0; i < n; i++) + env->mce_banks[i] = msrs[2 + i].data; + } + } +#endif + kvm_arch_save_mpstate(env); kvm_save_lapic(env); kvm_get_vcpu_events(env);