From patchwork Wed Feb 9 17:29:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 544551 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p19HWI7u027781 for ; Wed, 9 Feb 2011 17:32:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755294Ab1BIRbk (ORCPT ); Wed, 9 Feb 2011 12:31:40 -0500 Received: from tx2ehsobe003.messaging.microsoft.com ([65.55.88.13]:29929 "EHLO TX2EHSOBE006.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755120Ab1BIR3y (ORCPT ); Wed, 9 Feb 2011 12:29:54 -0500 Received: from mail85-tx2-R.bigfish.com (10.9.14.249) by TX2EHSOBE006.bigfish.com (10.9.40.26) with Microsoft SMTP Server id 14.1.225.8; Wed, 9 Feb 2011 17:29:53 +0000 Received: from mail85-tx2 (localhost.localdomain [127.0.0.1]) by mail85-tx2-R.bigfish.com (Postfix) with ESMTP id 029991688489; Wed, 9 Feb 2011 17:29:53 +0000 (UTC) X-SpamScore: -2 X-BigFish: VPS-2(zzbb2cKzz1202hzz8275bhz32i668h) X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:ausb3twp02.amd.com; RD:none; EFVD:NLI Received: from mail85-tx2 (localhost.localdomain [127.0.0.1]) by mail85-tx2 (MessageSwitch) id 1297272592752584_1772; Wed, 9 Feb 2011 17:29:52 +0000 (UTC) Received: from TX2EHSMHS021.bigfish.com (unknown [10.9.14.246]) by mail85-tx2.bigfish.com (Postfix) with ESMTP id B3D06DE804C; Wed, 9 Feb 2011 17:29:52 +0000 (UTC) Received: from ausb3twp02.amd.com (163.181.249.109) by TX2EHSMHS021.bigfish.com (10.9.99.121) with Microsoft SMTP Server id 14.1.225.8; Wed, 9 Feb 2011 17:29:52 +0000 X-WSS-ID: 0LGD1XN-02-4UK-02 X-M-MSG: Received: from sausexedgep01.amd.com (sausexedgep01-ext.amd.com [163.181.249.72]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp02.amd.com (Tumbleweed MailGate 3.7.2) with ESMTP id 2C43FC8ACB; Wed, 9 Feb 2011 11:29:47 -0600 (CST) Received: from sausexhtp02.amd.com (163.181.3.152) by sausexedgep01.amd.com (163.181.36.54) with Microsoft SMTP Server (TLS) id 8.3.106.1; Wed, 9 Feb 2011 11:30:44 -0600 Received: from storexhtp01.amd.com (172.24.4.3) by sausexhtp02.amd.com (163.181.3.152) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 9 Feb 2011 11:29:51 -0600 Received: from gwo.osrc.amd.com (165.204.16.204) by storexhtp01.amd.com (172.24.4.3) with Microsoft SMTP Server id 8.3.83.0; Wed, 9 Feb 2011 12:29:50 -0500 Received: from lemmy.osrc.amd.com (lemmy.osrc.amd.com [165.204.15.93]) by gwo.osrc.amd.com (Postfix) with ESMTP id ACFAD49C1A6; Wed, 9 Feb 2011 17:29:49 +0000 (GMT) Received: by lemmy.osrc.amd.com (Postfix, from userid 1000) id 93AB1FFBC2; Wed, 9 Feb 2011 18:29:49 +0100 (CET) From: Joerg Roedel To: Avi Kivity , Marcelo Tosatti CC: , , Zachary Amsden , Joerg Roedel Subject: [PATCH 2/6] KVM: SVM: Implement infrastructure for TSC_RATE_MSR Date: Wed, 9 Feb 2011 18:29:40 +0100 Message-ID: <1297272584-22689-3-git-send-email-joerg.roedel@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297272584-22689-1-git-send-email-joerg.roedel@amd.com> References: <1297272584-22689-1-git-send-email-joerg.roedel@amd.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 09 Feb 2011 17:32:18 +0000 (UTC) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 5bfafb6..fdac548 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -106,6 +106,7 @@ complete list. */ #define MSR_AMD64_PATCH_LEVEL 0x0000008b +#define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index bfb4948..c96c0a6 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -63,6 +63,8 @@ MODULE_LICENSE("GPL"); #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) +#define TSC_RATIO_RSVD 0xffffff0000000000ULL + static bool erratum_383_found __read_mostly; static const u32 host_save_user_msrs[] = { @@ -142,6 +144,12 @@ struct vcpu_svm { unsigned int3_injected; unsigned long int3_rip; u32 apf_reason; + + struct { + bool enabled; + u64 ratio; + } tsc_scale; + }; #define MSR_INVALID 0xffffffffU @@ -852,6 +860,25 @@ static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) seg->base = 0; } +static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) +{ + struct vcpu_svm *svm = to_svm(vcpu); + u64 _tsc = tsc; + + if (svm->tsc_scale.enabled) { + u64 mult, frac; + + mult = svm->tsc_scale.ratio >> 32; + frac = svm->tsc_scale.ratio & ((1ULL << 32) - 1); + + _tsc *= mult; + _tsc += (tsc >> 32) * frac; + _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; + } + + return _tsc; +} + static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) { struct vcpu_svm *svm = to_svm(vcpu); @@ -2808,7 +2835,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) case MSR_IA32_TSC: { struct vmcb *vmcb = get_host_vmcb(svm); - *data = vmcb->control.tsc_offset + native_read_tsc(); + *data = vmcb->control.tsc_offset + + svm_scale_tsc(vcpu, native_read_tsc()); + break; } case MSR_STAR: @@ -3564,6 +3593,9 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) clgi(); + if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && svm->tsc_scale.enabled) + wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_scale.ratio); + local_irq_enable(); asm volatile ( @@ -3647,6 +3679,9 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) local_irq_disable(); + if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && svm->tsc_scale.enabled) + wrmsr(MSR_AMD64_TSC_RATIO, 0, 1); + vcpu->arch.cr2 = svm->vmcb->save.cr2; vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;