From patchwork Fri Jun 17 13:37:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 891362 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p5HDbq15025990 for ; Fri, 17 Jun 2011 13:37:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758675Ab1FQNhU (ORCPT ); Fri, 17 Jun 2011 09:37:20 -0400 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16]:37342 "EHLO VA3EHSOBE009.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756951Ab1FQNhM (ORCPT ); Fri, 17 Jun 2011 09:37:12 -0400 Received: from mail158-va3-R.bigfish.com (10.7.14.243) by VA3EHSOBE009.bigfish.com (10.7.40.29) with Microsoft SMTP Server id 14.1.225.22; Fri, 17 Jun 2011 13:37:11 +0000 Received: from mail158-va3 (localhost.localdomain [127.0.0.1]) by mail158-va3-R.bigfish.com (Postfix) with ESMTP id 2B0CA19B83D1; Fri, 17 Jun 2011 13:37:11 +0000 (UTC) X-SpamScore: 1 X-BigFish: VPS1(zzzz1202hzz8275bhz32i668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:163.181.249.109; KIP:(null); UIP:(null); IPVD:NLI; H:ausb3twp02.amd.com; RD:none; EFVD:NLI Received: from mail158-va3 (localhost.localdomain [127.0.0.1]) by mail158-va3 (MessageSwitch) id 1308317830775578_12191; Fri, 17 Jun 2011 13:37:10 +0000 (UTC) Received: from VA3EHSMHS017.bigfish.com (unknown [10.7.14.240]) by mail158-va3.bigfish.com (Postfix) with ESMTP id AA8A0163004E; Fri, 17 Jun 2011 13:37:10 +0000 (UTC) Received: from ausb3twp02.amd.com (163.181.249.109) by VA3EHSMHS017.bigfish.com (10.7.99.27) with Microsoft SMTP Server id 14.1.225.22; Fri, 17 Jun 2011 13:37:05 +0000 X-WSS-ID: 0LMXSHO-02-52P-02 X-M-MSG: Received: from sausexedgep02.amd.com (sausexedgep02-ext.amd.com [163.181.249.73]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp02.amd.com (Axway MailGate 3.8.1) with ESMTP id 20B18C8325; Fri, 17 Jun 2011 08:37:00 -0500 (CDT) Received: from sausexhtp02.amd.com (163.181.3.152) by sausexedgep02.amd.com (163.181.36.59) with Microsoft SMTP Server (TLS) id 8.3.106.1; Fri, 17 Jun 2011 08:37:32 -0500 Received: from storexhtp01.amd.com (172.24.4.3) by sausexhtp02.amd.com (163.181.3.152) with Microsoft SMTP Server (TLS) id 8.3.83.0; Fri, 17 Jun 2011 08:37:02 -0500 Received: from gwo.osrc.amd.com (165.204.16.204) by storexhtp01.amd.com (172.24.4.3) with Microsoft SMTP Server id 8.3.83.0; Fri, 17 Jun 2011 09:37:01 -0400 Received: from lemmy.osrc.amd.com (lemmy.osrc.amd.com [165.204.15.93]) by gwo.osrc.amd.com (Postfix) with ESMTP id D7EB649C5EA; Fri, 17 Jun 2011 14:37:00 +0100 (BST) Received: by lemmy.osrc.amd.com (Postfix, from userid 1000) id 010D2FFEE5; Fri, 17 Jun 2011 15:37:36 +0200 (CEST) From: Joerg Roedel To: Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo CC: , , Joerg Roedel Subject: [PATCH 2/5] perf, amd: Use GO/HO bits in perf-ctr Date: Fri, 17 Jun 2011 15:37:31 +0200 Message-ID: <1308317854-27398-3-git-send-email-joerg.roedel@amd.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1308317854-27398-1-git-send-email-joerg.roedel@amd.com> References: <1308317854-27398-1-git-send-email-joerg.roedel@amd.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 17 Jun 2011 13:37:53 +0000 (UTC) The AMD perf-counters support counting in guest or host-mode only. Make use of that feature when user-space specified guest/host-mode only counting. Signed-off-by: Joerg Roedel --- arch/x86/include/asm/perf_event.h | 3 +++ arch/x86/kernel/cpu/perf_event_amd.c | 13 +++++++++++++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index d9d4dae..34047c2 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -29,6 +29,9 @@ #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL +#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40) +#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41) + #define AMD64_EVENTSEL_EVENT \ (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) #define INTEL_ARCH_EVENT_MASK \ diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index fe29c1d..66809e7 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c @@ -118,6 +118,19 @@ static int amd_pmu_hw_config(struct perf_event *event) if (ret) return ret; + if (event->attr.exclude_host && event->attr.exclude_guest) + /* + * When HO == GO == 1 the hardware treats that as GO == HO == 0 + * and will count in both modes. We don't want to count in that + * case so we emulate no-counting by setting US = OS = 0. + */ + event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR | + ARCH_PERFMON_EVENTSEL_OS); + else if (event->attr.exclude_host) + event->hw.config |= AMD_PERFMON_EVENTSEL_GUESTONLY; + else if (event->attr.exclude_guest) + event->hw.config |= AMD_PERFMON_EVENTSEL_HOSTONLY; + if (event->attr.type != PERF_TYPE_RAW) return 0;