From patchwork Thu Jul 28 17:56:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sasha Levin X-Patchwork-Id: 1017422 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6SHvG4o019462 for ; Thu, 28 Jul 2011 17:57:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753459Ab1G1R5N (ORCPT ); Thu, 28 Jul 2011 13:57:13 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:55820 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753076Ab1G1R5K (ORCPT ); Thu, 28 Jul 2011 13:57:10 -0400 Received: by mail-wy0-f174.google.com with SMTP id 8so327734wyg.19 for ; Thu, 28 Jul 2011 10:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=UtX3AsUSfGSh/x4cZgFp+cMvNQjcsBNtnu7+OztWA6Y=; b=MUnKjJUgYPj6hfRaBbsZGBayXQg0JgX2W4XrbhxwN6+mn69/0nQdjaA+NBIrteKZWO 9rWDdSdtqh/rQiqh4Q256WLUZswUoqG0x9RxkZ6FaPEjjtQdnkow6lkQqPCVPU52L9ni Z4o2k/gAUaO2gXArU/2QzO5Ib/B8IoRfSMexw= Received: by 10.227.181.9 with SMTP id bw9mr383698wbb.38.1311875830280; Thu, 28 Jul 2011 10:57:10 -0700 (PDT) Received: from localhost.localdomain (bzq-79-182-210-47.red.bezeqint.net [79.182.210.47]) by mx.google.com with ESMTPS id fp3sm1051561wbb.13.2011.07.28.10.57.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Jul 2011 10:57:09 -0700 (PDT) From: Sasha Levin To: penberg@kernel.org Cc: kvm@vger.kernel.org, mingo@elte.hu, asias.hejun@gmail.com, gorcunov@gmail.com, prasadjoshi124@gmail.com, Sasha Levin Subject: [PATCH v2 2/4] kvm tools: Fix PCI probing Date: Thu, 28 Jul 2011 20:56:19 +0300 Message-Id: <1311875781-691-2-git-send-email-levinsasha928@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1311875781-691-1-git-send-email-levinsasha928@gmail.com> References: <1311875781-691-1-git-send-email-levinsasha928@gmail.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 28 Jul 2011 17:57:16 +0000 (UTC) PCI BAR probing is done in four steps: 1. Read address (and flags). 2. Mask BAR. 3. Read BAR again - Now the expected result is the size of the BAR. 4. Mask BAR with address. So far, we have only took care of the first step. This means that the kernel was using address as the size, causing a PCI allocation blunder. This patch fixes the issue by passing a proper size after masking. Signed-off-by: Sasha Levin --- tools/kvm/include/kvm/pci.h | 1 + tools/kvm/pci.c | 60 +++++++++++++++++++++++++++++++++++++++--- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/tools/kvm/include/kvm/pci.h b/tools/kvm/include/kvm/pci.h index 6ad4426..a7532e3 100644 --- a/tools/kvm/include/kvm/pci.h +++ b/tools/kvm/include/kvm/pci.h @@ -51,5 +51,6 @@ struct pci_device_header { void pci__init(void); void pci__register(struct pci_device_header *dev, u8 dev_num); +u32 pci_get_io_space_block(void); #endif /* KVM__PCI_H */ diff --git a/tools/kvm/pci.c b/tools/kvm/pci.c index a1ad8ba..3b92ea4 100644 --- a/tools/kvm/pci.c +++ b/tools/kvm/pci.c @@ -1,15 +1,29 @@ #include "kvm/pci.h" #include "kvm/ioport.h" #include "kvm/util.h" +#include "kvm/kvm.h" #include #define PCI_MAX_DEVICES 256 +#define PCI_IO_SIZE 0x100 +#define PCI_BAR_OFFSET(b) (offsetof(struct pci_device_header, bar[b])) static struct pci_device_header *pci_devices[PCI_MAX_DEVICES]; static struct pci_config_address pci_config_address; +/* This is within our PCI gap - in an unused area */ +static u32 io_space_blocks = KVM_32BIT_GAP_START + 0x1000000; + +u32 pci_get_io_space_block(void) +{ + u32 block = io_space_blocks; + io_space_blocks += PCI_IO_SIZE; + + return block; +} + static void *pci_config_address_ptr(u16 port) { unsigned long offset; @@ -44,11 +58,6 @@ static struct ioport_operations pci_config_address_ops = { .io_out = pci_config_address_out, }; -static bool pci_config_data_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size, u32 count) -{ - return true; -} - static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number) { struct pci_device_header *dev; @@ -67,6 +76,47 @@ static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_numbe return dev != NULL; } +static bool pci_config_data_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size, u32 count) +{ + unsigned long start; + u8 dev_num; + + /* + * If someone accesses PCI configuration space offsets that are not + * aligned to 4 bytes, it uses ioports to signify that. + */ + start = port - PCI_CONFIG_DATA; + + dev_num = pci_config_address.device_number; + + if (pci_device_exists(0, dev_num, 0)) { + unsigned long offset; + + offset = start + (pci_config_address.register_number << 2); + if (offset < sizeof(struct pci_device_header)) { + void *p = pci_devices[dev_num]; + u32 sz = PCI_IO_SIZE; + + /* + * If the kernel masks the BAR it would expect to find the + * size of the BAR there next time it reads from it. + * When the kernel got the size it would write the address + * back. + */ + if (*(u32 *)(p + offset)) { + /* See if kernel tries to mask one of the BARs */ + if ((offset >= PCI_BAR_OFFSET(0)) && + (offset <= PCI_BAR_OFFSET(6))) + memcpy(p + offset, &sz, sizeof(sz)); + else + memcpy(p + offset, data, size); + } + } + } + + return true; +} + static bool pci_config_data_in(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size, u32 count) { unsigned long start;