From patchwork Mon Aug 8 13:08:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 1044322 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p78DArQj030035 for ; Mon, 8 Aug 2011 13:11:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754518Ab1HHNK7 (ORCPT ); Mon, 8 Aug 2011 09:10:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:62558 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754009Ab1HHNJi (ORCPT ); Mon, 8 Aug 2011 09:09:38 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p78D9all012026 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 8 Aug 2011 09:09:36 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p78D9Zw2030050; Mon, 8 Aug 2011 09:09:35 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id 0E4D8250B48; Mon, 8 Aug 2011 16:09:34 +0300 (IDT) From: Avi Kivity To: Anthony Liguori , qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , kvm@vger.kernel.org Subject: [PATCH v4 06/39] cirrus: simplify bitblt BAR access functions Date: Mon, 8 Aug 2011 16:08:59 +0300 Message-Id: <1312808972-1718-7-git-send-email-avi@redhat.com> In-Reply-To: <1312808972-1718-1-git-send-email-avi@redhat.com> References: <1312808972-1718-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 08 Aug 2011 13:11:09 +0000 (UTC) Make use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses. Reviewed-by: Richard Henderson Reviewed-by: Anthony Liguori Signed-off-by: Avi Kivity --- hw/cirrus_vga.c | 81 +++++++++---------------------------------------------- 1 files changed, 13 insertions(+), 68 deletions(-) diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 4f57b92..c39acb9 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -2446,37 +2446,23 @@ static void cirrus_linear_write(void *opaque, target_phys_addr_t addr, ***************************************/ -static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr) +static uint64_t cirrus_linear_bitblt_read(void *opaque, + target_phys_addr_t addr, + unsigned size) { + CirrusVGAState *s = opaque; uint32_t ret; /* XXX handle bitblt */ + (void)s; ret = 0xff; return ret; } -static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) -{ - uint32_t v; - - v = cirrus_linear_bitblt_readb(opaque, addr); - v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; - return v; -} - -static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) -{ - uint32_t v; - - v = cirrus_linear_bitblt_readb(opaque, addr); - v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; - v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16; - v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24; - return v; -} - -static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, - uint32_t val) +static void cirrus_linear_bitblt_write(void *opaque, + target_phys_addr_t addr, + uint64_t val, + unsigned size) { CirrusVGAState *s = opaque; @@ -2489,55 +2475,14 @@ static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); - cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); -} - -static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); - cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); - cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff); - cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff); -} - -static uint64_t cirrus_linear_bitblt_read(void *opaque, - target_phys_addr_t addr, - unsigned size) -{ - CirrusVGAState *s = opaque; - - switch (size) { - case 1: return cirrus_linear_bitblt_readb(s, addr); - case 2: return cirrus_linear_bitblt_readw(s, addr); - case 4: return cirrus_linear_bitblt_readl(s, addr); - default: abort(); - } -}; - -static void cirrus_linear_bitblt_write(void *opaque, - target_phys_addr_t addr, - uint64_t data, - unsigned size) -{ - CirrusVGAState *s = opaque; - - switch (size) { - case 1: return cirrus_linear_bitblt_writeb(s, addr, data); - case 2: return cirrus_linear_bitblt_writew(s, addr, data); - case 4: return cirrus_linear_bitblt_writel(s, addr, data); - default: abort(); - } -}; - static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { .read = cirrus_linear_bitblt_read, .write = cirrus_linear_bitblt_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, }; static void unmap_bank(CirrusVGAState *s, unsigned bank)