diff mbox

kvm-tool: ARM: set interrupt priority mask in secondary boot path

Message ID 1354204713-17905-1-git-send-email-marc.zyngier@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Marc Zyngier Nov. 29, 2012, 3:58 p.m. UTC
A bug in the KVM GIC init code set the priority mask to the
highest possible value, while the reset value should be zero.

Now that the kernel bug is fixed, kvm-tool must properly configure
its GIC CPU interface in order to receive the boot IPI.  Just set
the GICC_PMR register to the maximum value (0xff), and it "just works".

Cc: Will Deacon <will.deacon@arm.com>
Cc: Pekka Enberg <penberg@kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 tools/kvm/arm/aarch32/smp-pen.S        | 4 ++++
 tools/kvm/arm/include/arm-common/gic.h | 2 ++
 2 files changed, 6 insertions(+)

Comments

Peter Maydell Nov. 29, 2012, 4:02 p.m. UTC | #1
On 29 November 2012 15:58, Marc Zyngier <marc.zyngier@arm.com> wrote:
> A bug in the KVM GIC init code set the priority mask to the
> highest possible value, while the reset value should be zero.
>
> Now that the kernel bug is fixed, kvm-tool must properly configure
> its GIC CPU interface in order to receive the boot IPI.  Just set
> the GICC_PMR register to the maximum value (0xff), and it "just works".

> --- a/tools/kvm/arm/include/arm-common/gic.h
> +++ b/tools/kvm/arm/include/arm-common/gic.h
> @@ -20,6 +20,8 @@
>
>  #define GIC_CPUI_CTLR_EN               (1 << 0)
>
> +#define GIC_CPUI_DEFAULT_PMR           0xff

This seems an odd name, since 0xff is not the default, which is
why we have to write it into the register. Also the register
name should presumably go after CPUI, to match CTLR above.
GIC_CPUI_PMR_MINIMUM_PRIORITY ?

-- PMM
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diff mbox

Patch

diff --git a/tools/kvm/arm/aarch32/smp-pen.S b/tools/kvm/arm/aarch32/smp-pen.S
index 0861171..cee1d3b8 100644
--- a/tools/kvm/arm/aarch32/smp-pen.S
+++ b/tools/kvm/arm/aarch32/smp-pen.S
@@ -17,6 +17,10 @@  smp_pen_start:
 	mov	r1, #GIC_CPUI_CTLR_EN
 	str	r1, [r0]
 
+	@ Set the priority mask to accept any interrupt
+	mov	r1, #GIC_CPUI_DEFAULT_PMR
+	str	r1, [r0, #4]
+
 	@ Now wait for the primary to poke us
 	adr	r0, smp_jump_addr
 	ldr	r1, =AARCH32_SMP_BAD_MAGIC
diff --git a/tools/kvm/arm/include/arm-common/gic.h b/tools/kvm/arm/include/arm-common/gic.h
index d534174..6fa806f 100644
--- a/tools/kvm/arm/include/arm-common/gic.h
+++ b/tools/kvm/arm/include/arm-common/gic.h
@@ -20,6 +20,8 @@ 
 
 #define GIC_CPUI_CTLR_EN		(1 << 0)
 
+#define GIC_CPUI_DEFAULT_PMR		0xff
+
 #define GIC_MAX_CPUS			8
 #define GIC_MAX_IRQ			255