From patchwork Thu Feb 7 19:42:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 2113061 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 8B0C23FDF1 for ; Thu, 7 Feb 2013 19:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422688Ab3BGTnp (ORCPT ); Thu, 7 Feb 2013 14:43:45 -0500 Received: from mail-da0-f42.google.com ([209.85.210.42]:35105 "EHLO mail-da0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422639Ab3BGTno (ORCPT ); Thu, 7 Feb 2013 14:43:44 -0500 Received: by mail-da0-f42.google.com with SMTP id z17so1412644dal.29 for ; Thu, 07 Feb 2013 11:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=x/ZEH/QZO8THtPcAQNJlgcCSEWTEdzjh18h0FVER7So=; b=PkmI8ONiG8NntCHM031cdTV2G1DqZDhhdfWEunihpvo1VH/6jORYr3fAPdHMXhZ5vE KePfeEHivt1ngo77spePpzBVlPuEH726tsW3dsNID23AEITE0BfOyvvQwmYJa6/1/20L NoVjYs21ThGojbk3zvHwUBadr2eSGUP5NdATVwZUO8OJu+7rI2S7eo8ttAuPdusOLWEM X9XXS5WrrzahUBik34sP0+sPS/hIpRuwCNTY7LaWLI6xbD4FZF4KDQfqI2G2uQfcBBtD g7BUfkyAImCBBZMuJ5j6HxZzBOR6io9XJLevd4vhFtIVzPv3TVUDFdgftF4a+Gx86oC2 yX4A== X-Received: by 10.66.83.165 with SMTP id r5mr9095407pay.3.1360266224039; Thu, 07 Feb 2013 11:43:44 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id o5sm48216756pay.5.2013.02.07.11.43.42 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 07 Feb 2013 11:43:43 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r17JgfFS017797; Thu, 7 Feb 2013 11:42:41 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r17JgcfJ017795; Thu, 7 Feb 2013 11:42:38 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Sanjay Lal , kvm@vger.kernel.org Subject: [RFC PATCH] MIPS/kvm: Add asm/kvm.h Date: Thu, 7 Feb 2013 11:42:34 -0800 Message-Id: <1360266154-17761-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: David Daney Uniform definitions for both 32-bit and 64-bit MIPS machines. Signed-off-by: David Daney Cc: Sanjay Lal Cc: kvm@vger.kernel.org --- Previously Sanjay posted a version of asm/kvm.h that worked only for 32-bit MIPS machines. Since the MIPS kernel port also supports 64-bit CPUs, we need a virtual machine interface that can handle both 32 and 64 bit environments. Surly we will need to extend this, but I thought it may be a good starting point for future enhancements. Please comment. arch/mips/include/uapi/asm/kvm.h | 94 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 arch/mips/include/uapi/asm/kvm.h diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h new file mode 100644 index 0000000..caca51d --- /dev/null +++ b/arch/mips/include/uapi/asm/kvm.h @@ -0,0 +1,94 @@ +#ifndef _ASM_MIPS_KVM_H +#define _ASM_MIPS_KVM_H +/* + * KVM MIPS specific structures and definitions. + * + * Some parts derived from the x86 version of this file. + */ + +/* for KVM_GET_REGS and KVM_SET_REGS */ +/* + * If Config[AT] is zero (32-bit CPU), the register contents are + * stored in the lower 32-bits of the struct kvm_regs fields and sign + * extended to 64-bits. + */ +struct kvm_regs { + /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ + __u64 gpr[32]; + __u64 hi, lo; + __u64 pc; +}; + +/* for KVM_GET_FPU and KVM_SET_FPU */ +/* + * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs + * are zero filled. + */ +struct kvm_fpu { + __u64 fpr[32]; + __u32 fir; + __u32 fccr; + __u32 fexr; + __u32 fenr; + __u32 fcsr; + __u32 pad; +}; + + +/* + * For MIPS, we use the same APIs as x86, where 'msr' corresponds to a + * CP0 register. The index field is broken down as follows: + * + * bits[2..0] - Register 'sel' index. + * bits[7..3] - Register 'rd' index. + * bits[15..8] - Must be zero. + * bits[31..16] - 0 -> CP0 registers. + * + * Other sets registers may be added in the future. Each set would + * have its own identifier in bits[31..16]. + * + * For MSRs that are narrower than 64-bits, the value is stored in the + * low order bits of the data field, and sign extended to 64-bits. + */ +#define KVM_MIPS_MSR_CP0 0 +struct kvm_msr_entry { + __u32 index; + __u32 reserved; + __u64 data; +}; + +/* for KVM_GET_MSRS and KVM_SET_MSRS */ +struct kvm_msrs { + __u32 nmsrs; /* number of msrs in entries */ + __u32 pad; + + struct kvm_msr_entry entries[0]; +}; + +/* for KVM_GET_MSR_INDEX_LIST */ +struct kvm_msr_list { + __u32 nmsrs; /* number of msrs in entries */ + __u32 indices[0]; +}; + +/* + * KVM MIPS specific structures and definitions + * + */ +struct kvm_debug_exit_arch { + __u64 epc; +}; + +/* for KVM_SET_GUEST_DEBUG */ +struct kvm_guest_debug_arch { +}; + +/* definition of registers in kvm_run */ +struct kvm_sync_regs { +}; + +/* dummy definition */ +struct kvm_sregs { +}; + +#endif /* _ASM_MIPS_KVM_H */