From patchwork Sat Mar 2 15:18:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjay Lal X-Patchwork-Id: 2207161 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 94274DFF33 for ; Sat, 2 Mar 2013 15:18:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752209Ab3CBPSw (ORCPT ); Sat, 2 Mar 2013 10:18:52 -0500 Received: from kymasys.com ([64.62.140.43]:46378 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1751962Ab3CBPSv (ORCPT ); Sat, 2 Mar 2013 10:18:51 -0500 Received: from agni.kymasys.com ([75.40.23.192]) by kymasys.com for ; Sat, 2 Mar 2013 07:18:50 -0800 Received: by agni.kymasys.com (Postfix, from userid 500) id E2EF763003E; Sat, 2 Mar 2013 07:18:49 -0800 (PST) From: Sanjay Lal To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Gleb Natapov , Marcelo Tosatti , Sanjay Lal Subject: [Qemu-devel][PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP Date: Sat, 2 Mar 2013 07:18:35 -0800 Message-Id: <1362237527-23678-2-git-send-email-sanjayl@kymasys.com> X-Mailer: git-send-email 1.7.11.3 In-Reply-To: <1362237527-23678-1-git-send-email-sanjayl@kymasys.com> References: <1362237527-23678-1-git-send-email-sanjayl@kymasys.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org --- hw/mips_cps_bootcode.h | 310 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 310 insertions(+) create mode 100644 hw/mips_cps_bootcode.h diff --git a/hw/mips_cps_bootcode.h b/hw/mips_cps_bootcode.h new file mode 100644 index 0000000..40289a4 --- /dev/null +++ b/hw/mips_cps_bootcode.h @@ -0,0 +1,310 @@ +/* Sample boot code for 1004K CPS (Coherent Processing System.) + * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors + * + * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved. + */ + +#ifndef __MIPS_CPS_BOOTCODE_H__ +#define __MIPS_CPS_BOOTCODE_H__ + +#ifdef TARGET_WORDS_BIGENDIAN +#error CPS bootcode for MIPS Big Endian target not available yet +#else +static unsigned char __boot_cps_data[] = { + 0x3f,0x01,0x00,0x10,0x00,0x48,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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