From patchwork Tue Mar 5 03:47:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 2216891 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 0246E3FCF6 for ; Tue, 5 Mar 2013 03:56:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933181Ab3CEDz6 (ORCPT ); Mon, 4 Mar 2013 22:55:58 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:54948 "EHLO inca-roads.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933067Ab3CEDz6 (ORCPT ); Mon, 4 Mar 2013 22:55:58 -0500 Received: from [118.143.64.134] (helo=why.wild-wind.fr.eu.org) by inca-roads.misterjones.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1UCisE-0002NK-9T; Tue, 05 Mar 2013 04:49:06 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: catalin.marinas@arm.com Subject: [PATCH 26/29] arm64: KVM: 32bit coprocessor access for Cortex-A57 Date: Tue, 5 Mar 2013 03:47:42 +0000 Message-Id: <1362455265-24165-27-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1362455265-24165-1-git-send-email-marc.zyngier@arm.com> References: <1362455265-24165-1-git-send-email-marc.zyngier@arm.com> X-SA-Exim-Connect-IP: 118.143.64.134 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, catalin.marinas@arm.com X-SA-Exim-Mail-From: marc.zyngier@arm.com X-SA-Exim-Scanned: No (on inca-roads.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable handling of 32bit coprocessor traps for Cortex-A57. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs_a57.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/kvm/sys_regs_a57.c b/arch/arm64/kvm/sys_regs_a57.c index dcc88fe..56c0641 100644 --- a/arch/arm64/kvm/sys_regs_a57.c +++ b/arch/arm64/kvm/sys_regs_a57.c @@ -59,6 +59,17 @@ static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) vcpu->arch.sys_regs[ACTLR_EL1] = actlr; } +static bool access_ectlr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt) = 0; + return true; +} + /* * A57-specific sys-reg registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -74,12 +85,23 @@ static const struct sys_reg_desc a57_sys_regs[] = { NULL, reset_val, CPACR_EL1, 0 }, }; +static const struct sys_reg_desc a57_cp15_regs[] = { + { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001), /* ACTLR */ + access_actlr }, + { Op1(0b001), CRn(0b0000), CRm(0b1111), Op2(0b000), /* ECTLR */ + access_ectlr }, +}; + static struct kvm_sys_reg_target_table a57_target_table = { .target = KVM_ARM_TARGET_CORTEX_A57, .table64 = { .table = a57_sys_regs, .num = ARRAY_SIZE(a57_sys_regs), }, + .table32 = { + .table = a57_cp15_regs, + .num = ARRAY_SIZE(a57_cp15_regs), + }, }; static int __init sys_reg_a57_init(void)