From patchwork Fri Mar 15 07:26:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 2275121 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 1E8744020C for ; Fri, 15 Mar 2013 07:26:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752363Ab3COH0s (ORCPT ); Fri, 15 Mar 2013 03:26:48 -0400 Received: from e36.co.us.ibm.com ([32.97.110.154]:60592 "EHLO e36.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751724Ab3COH0r (ORCPT ); Fri, 15 Mar 2013 03:26:47 -0400 Received: from /spool/local by e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 15 Mar 2013 01:26:46 -0600 Received: from d03dlp03.boulder.ibm.com (9.17.202.179) by e36.co.us.ibm.com (192.168.1.136) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 15 Mar 2013 01:26:44 -0600 Received: from d03relay05.boulder.ibm.com (d03relay05.boulder.ibm.com [9.17.195.107]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 0FDD019D8045 for ; Fri, 15 Mar 2013 01:26:41 -0600 (MDT) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay05.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r2F7Qe5g173638 for ; Fri, 15 Mar 2013 01:26:41 -0600 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r2F7QbAd014464 for ; Fri, 15 Mar 2013 01:26:40 -0600 Received: from shangw ([9.77.179.176]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r2F7QZNX014373; Fri, 15 Mar 2013 01:26:36 -0600 Received: by shangw (Postfix, from userid 1000) id B66333021F9; Fri, 15 Mar 2013 15:26:33 +0800 (CST) From: Gavin Shan To: kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: alex.williamson@redhat.com, benh@kernel.crashing.org, aik@ozlabs.ru, Gavin Shan Subject: [PATCH 3/3] VFIO: Direct access config reg without capability Date: Fri, 15 Mar 2013 15:26:30 +0800 Message-Id: <1363332390-12754-4-git-send-email-shangw@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1363332390-12754-1-git-send-email-shangw@linux.vnet.ibm.com> References: <1363332390-12754-1-git-send-email-shangw@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13031507-7606-0000-0000-00000977933D Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The config registers in [0, 0x40] is being supported by VFIO. Apart from that, the other config registers should be coverred by PCI or PCIe capability. However, there might have some PCI devices (be2net) who has config registers (0x7c) out of [0, 0x40], and don't have corresponding PCI or PCIe capability. VFIO will return 0x0 on reading those registers and writing is dropped. It caused the be2net driver fails to be loaded because 0x0 returned from its config register 0x7c. The patch changes the behaviour so that those config registers out of [0, 0x40] and don't have corresponding PCI or PCIe capability will be accessed directly. Signed-off-by: Gavin Shan --- drivers/vfio/pci/vfio_pci_config.c | 31 ++++++++++++++++++++----------- 1 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 964ff22..5ea3afb 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -1471,18 +1471,27 @@ static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, cap_id = vdev->pci_config_map[*ppos / 4]; + /* + * Some PCI device config registers might not be coverred by + * capability and useful. We will enable direct access to + * those registers. + */ if (cap_id == PCI_CAP_ID_INVALID) { - if (iswrite) - return ret; /* drop */ - - /* - * Per PCI spec 3.0, section 6.1, reads from reserved and - * unimplemented registers return 0 - */ - if (copy_to_user(buf, &val, count)) - return -EFAULT; - - return ret; + if (iswrite) { + if (copy_from_user(&val, buf, count)) + return -EFAULT; + ret = vfio_user_config_write(vdev->pdev, (int)(*ppos), + val, count); + return ret ? ret : count; + } else { + ret = vfio_user_config_read(vdev->pdev, (int)(*ppos), + &val, count); + if (ret) + return ret; + if (copy_to_user(buf, &val, count)) + return -EFAULT; + return count; + } } /*