From patchwork Mon Jun 10 13:45:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arthur Chunqi Li X-Patchwork-Id: 2697611 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 3F289DF264 for ; Mon, 10 Jun 2013 13:45:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750861Ab3FJNpV (ORCPT ); Mon, 10 Jun 2013 09:45:21 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:56357 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750695Ab3FJNpU (ORCPT ); Mon, 10 Jun 2013 09:45:20 -0400 Received: by mail-pa0-f51.google.com with SMTP id lf11so1805097pab.38 for ; Mon, 10 Jun 2013 06:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=A2maiVXmyENXl8+zf+Z8WkQSdkpo/7ngcg7uluwJGbs=; b=ntD/U470UnrS7F5rLu4rHgRW9nOBzySv6rCKjuIxz1YPAqSlILC0+C/DLeX7jVbjKo Fv3ZxHWHzhVga9HURT7KNlqPkkQE+STab1yr/gneFE6s4rOqzOqfXPIIrrNtmSiCdZMI lr9Ia+ZxIY2F3hJ0W3AVNXQvy8XajLGp1VGdv1rayOWsCQXIARCcgudedn/RsCA3hdcg T2glojziZikVBxh6BYxrmfEG80DN2W4jQwGt5TwwWZU+Ickb6FjlezN68jKcbVxjMzwc Blw+CEAw17SnpLkXFz7h6ierCUt1GWmturmJRshwW+U054wY4a3rEDdPIbpTBFpx+Ama tOPg== X-Received: by 10.66.240.103 with SMTP id vz7mr3635147pac.194.1370871919934; Mon, 10 Jun 2013 06:45:19 -0700 (PDT) Received: from Blade1-02.Blade1-02 ([162.105.146.101]) by mx.google.com with ESMTPSA id vb8sm10562310pbc.11.2013.06.10.06.45.16 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 10 Jun 2013 06:45:18 -0700 (PDT) From: Arthur Chunqi Li To: kvm@vger.kernel.org Cc: gleb@redhat.com, pbonzini@redhat.com, Arthur Chunqi Li Subject: [PATCH 2/2] kvm-unit-tests: Change two cases to use trap_emulator Date: Mon, 10 Jun 2013 21:45:04 +0800 Message-Id: <1370871904-32049-1-git-send-email-yzt356@gmail.com> X-Mailer: git-send-email 1.7.9.5 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Change two functions (test_mmx_movq_mf and test_movabs) using unified trap_emulator. Signed-off-by: Arthur Chunqi Li --- x86/emulator.c | 63 +++++++++++--------------------------------------------- 1 file changed, 12 insertions(+), 51 deletions(-) diff --git a/x86/emulator.c b/x86/emulator.c index a1bd92e..c73c766 100644 --- a/x86/emulator.c +++ b/x86/emulator.c @@ -801,36 +801,17 @@ static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, uint8_t *alt_insn_page, void *insn_ram) { uint16_t fcw = 0; // all exceptions unmasked - ulong *cr3 = (ulong *)read_cr3(); + uint8_t alt_insn[] = {0x0f, 0x7f, 0x00}; // movq %mm0, (%rax) write_cr0(read_cr0() & ~6); // TS, EM - // Place a trapping instruction in the page to trigger a VMEXIT - insn_page[0] = 0x89; // mov %eax, (%rax) - insn_page[1] = 0x00; - insn_page[2] = 0x90; // nop - insn_page[3] = 0xc3; // ret - // Place the instruction we want the hypervisor to see in the alternate page - alt_insn_page[0] = 0x0f; // movq %mm0, (%rax) - alt_insn_page[1] = 0x7f; - alt_insn_page[2] = 0x00; - alt_insn_page[3] = 0xc3; // ret - exceptions = 0; handle_exception(MF_VECTOR, advance_rip_by_3_and_note_exception); - - // Load the code TLB with insn_page, but point the page tables at - // alt_insn_page (and keep the data TLB clear, for AMD decode assist). - // This will make the CPU trap on the insn_page instruction but the - // hypervisor will see alt_insn_page. - install_page(cr3, virt_to_phys(insn_page), insn_ram); asm volatile("fninit; fldcw %0" : : "m"(fcw)); asm volatile("fldz; fldz; fdivp"); // generate exception - invlpg(insn_ram); - // Load code TLB - asm volatile("call *%0" : : "r"(insn_ram + 3)); - install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); - // Trap, let hypervisor emulate at alt_insn_page - asm volatile("call *%0" : : "r"(insn_ram), "a"(mem)); + + inregs = (struct regs){ 0 }; + trap_emulator(mem, insn_page, alt_insn_page, insn_ram, + alt_insn, 3, 1); // exit MMX mode asm volatile("fnclex; emms"); report("movq mmx generates #MF", exceptions == 1); @@ -840,33 +821,13 @@ static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, static void test_movabs(uint64_t *mem, uint8_t *insn_page, uint8_t *alt_insn_page, void *insn_ram) { - uint64_t val = 0; - ulong *cr3 = (ulong *)read_cr3(); - - // Pad with RET instructions - memset(insn_page, 0xc3, 4096); - memset(alt_insn_page, 0xc3, 4096); - // Place a trapping instruction in the page to trigger a VMEXIT - insn_page[0] = 0x89; // mov %eax, (%rax) - insn_page[1] = 0x00; - // Place the instruction we want the hypervisor to see in the alternate - // page. A buggy hypervisor will fetch a 32-bit immediate and return - // 0xffffffffc3c3c3c3. - alt_insn_page[0] = 0x48; // mov $0xc3c3c3c3c3c3c3c3, %rcx - alt_insn_page[1] = 0xb9; - - // Load the code TLB with insn_page, but point the page tables at - // alt_insn_page (and keep the data TLB clear, for AMD decode assist). - // This will make the CPU trap on the insn_page instruction but the - // hypervisor will see alt_insn_page. - install_page(cr3, virt_to_phys(insn_page), insn_ram); - // Load code TLB - invlpg(insn_ram); - asm volatile("call *%0" : : "r"(insn_ram + 3)); - // Trap, let hypervisor emulate at alt_insn_page - install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); - asm volatile("call *%1" : "=c"(val) : "r"(insn_ram), "a"(mem), "c"(0)); - report("64-bit mov imm", val == 0xc3c3c3c3c3c3c3c3); + // mov $0xc3c3c3c3c3c3c3c3, %rcx + uint8_t alt_insn[] = {0x48, 0xb9, 0xc3, 0xc3, 0xc3, + 0xc3, 0xc3, 0xc3, 0xc3, 0xc3}; + inregs = (struct regs){ .rcx = 0 }; + trap_emulator(mem, insn_page, alt_insn_page, insn_ram, + alt_insn, 10, 1); + report("64-bit mov imm2", outregs.rcx == 0xc3c3c3c3c3c3c3c3); } static void test_crosspage_mmio(volatile uint8_t *mem)