From patchwork Tue Jun 11 04:51:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 2699891 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 36C7ADF23A for ; Tue, 11 Jun 2013 04:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753830Ab3FKEw3 (ORCPT ); Tue, 11 Jun 2013 00:52:29 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:53369 "EHLO mail-pd0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753737Ab3FKEw2 (ORCPT ); Tue, 11 Jun 2013 00:52:28 -0400 Received: by mail-pd0-f171.google.com with SMTP id y14so5301944pdi.30 for ; Mon, 10 Jun 2013 21:52:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=KxmPkbJXYVB6oc6bJydwO4TO3T5HeudVw1s6R+X6cDE=; b=mg0EcUVA4pXFfjtclBylv8SIZpmwoAhhFz9fVpmlRfMlHTfjerUJOpiSu8qj9xfj8H Jv52xEp+LGL+bTf8MCK8Mt2WOctEO3RbtI59piGiY/yQN+++G9MTBHzo4D7xQMLX3nni 9Gkhj9hjY4z7bPu9KU2YKmGs+b6EtfH2ztkjEVDHZ8iqDYaD3eH/B5T4CR3GiAjvebo9 8EgYrCVsNRazaW1mTQetAcz26UTLCbOhT+voQ1X/pZ3qHzcupuUxx47TaFLpj0eVQquG EfR/tSTwFkD7DRbIpiOXdJv0g43CuiDJiyXPYQsQyUs3JF+WUI+dhWvx4bB9AvT1Wivo GRhw== X-Received: by 10.68.130.199 with SMTP id og7mr13063152pbb.132.1370926347900; Mon, 10 Jun 2013 21:52:27 -0700 (PDT) Received: from localhost.localdomain (c-67-169-183-77.hsd1.ca.comcast.net. [67.169.183.77]) by mx.google.com with ESMTPSA id i16sm18268008pag.18.2013.06.10.21.52.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 10 Jun 2013 21:52:26 -0700 (PDT) From: Christoffer Dall To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: patches@linaro.org, linaro-kernel@lists.linaro.org, Christoffer Dall Subject: [PATCH 7/7] KVM: arm-vgic: Support CPU interface reg access Date: Mon, 10 Jun 2013 21:51:19 -0700 Message-Id: <1370926279-32532-8-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370926279-32532-1-git-send-email-christoffer.dall@linaro.org> References: <1370926279-32532-1-git-send-email-christoffer.dall@linaro.org> X-Gm-Message-State: ALoCoQmMzXa5wz5V1AZJCtSiBJtvaTAB2eFEzIB720YFCfA4KznAs4E6W+W9v2Eg3Efm+NV+uAxz Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Implement support for the CPU interface register access driven by MMIO address offsets from the CPU interface base address. Useful for user space to support save/restore of the VGIC state. This commit adds support only for the same logic as the current VGIC support, and no more. For example, the active priority registers are handled as RAZ/WI, just like setting priorities on the emulated distributor. Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 3 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 62d0fec..64bea93 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -1660,9 +1660,61 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { - return true; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u32 reg, mask = 0, shift = 0; + bool updated = false; + + switch (offset & ~0x3) { + case GIC_CPU_CTRL: + mask = GICH_VMCR_CTRL_MASK; + shift = GICH_VMCR_CTRL_SHIFT; + break; + case GIC_CPU_PRIMASK: + mask = GICH_VMCR_PRIMASK_MASK; + shift = GICH_VMCR_PRIMASK_SHIFT; + break; + case GIC_CPU_BINPOINT: + mask = GICH_VMCR_BINPOINT_MASK; + shift = GICH_VMCR_BINPOINT_SHIFT; + break; + case GIC_CPU_ALIAS_BINPOINT: + mask = GICH_VMCR_ALIAS_BINPOINT_MASK; + shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT; + break; + } + + if (!mmio->is_write) { + reg = (vgic_cpu->vgic_vmcr & mask) >> 0; + memcpy(mmio->data, ®, sizeof(reg)); + } else { + memcpy(®, mmio->data, sizeof(reg)); + reg = (reg << shift) & mask; + if (reg != (vgic_cpu->vgic_vmcr & mask)) + updated = true; + vgic_cpu->vgic_vmcr &= ~mask; + vgic_cpu->vgic_vmcr |= reg; + } + return updated; } +static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + u32 reg; + + if (mmio->is_write) + return false; + + reg = 0x0002043B; + memcpy(mmio->data, ®, sizeof(reg)); + return false; +} + +/* + * CPU Interface Register accesses - these are not accessed by the VM, but by + * user space for saving and restoring VGIC state. + */ static const struct mmio_range vgic_cpu_ranges[] = { { .base = GIC_CPU_CTRL, @@ -1687,12 +1739,12 @@ static const struct mmio_range vgic_cpu_ranges[] = { { .base = GIC_CPU_ACTIVEPRIO, .len = 16, - .handle_mmio = handle_cpu_mmio_misc, + .handle_mmio = handle_mmio_raz_wi, }, { .base = GIC_CPU_IDENT, .len = 4, - .handle_mmio = handle_cpu_mmio_misc, + .handle_mmio = handle_cpu_mmio_ident, }, };