From patchwork Thu Jun 20 14:36:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arthur Chunqi Li X-Patchwork-Id: 2756501 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 74E279F751 for ; Thu, 20 Jun 2013 14:36:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 289B420171 for ; Thu, 20 Jun 2013 14:36:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C439201BA for ; Thu, 20 Jun 2013 14:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757607Ab3FTOgh (ORCPT ); Thu, 20 Jun 2013 10:36:37 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:56132 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757483Ab3FTOgg (ORCPT ); Thu, 20 Jun 2013 10:36:36 -0400 Received: by mail-pb0-f46.google.com with SMTP id rq2so6290980pbb.33 for ; Thu, 20 Jun 2013 07:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=dZ8Fm8qK1IxPMK6Hq0mgXc/sLpmI8EK9/t3C7lYw58E=; b=LIfpdYBndUJghGWVgvgLTTMSKT6ZMpMuadB8Ni6JT9LGzC8ulA7U9PL6qZaBWAJgQv lkeshOAtVUUb9qzocpANKs5w11JhhkEVkBy6GQS48iFiMXpbLmSYMfXk0Jo/eJb5kn3n LMbPkQchKieeOrcM1RAP08PLW0OYzUoXeaNIK9E6vATx6ejx6ewzqJc2KuLR9VWmdp7A 0tWSkJbj7ojOR0DTfpB0MsK13x61NDIcVL7GyaSyGM8J2yQbbzydmU9TpncMSTuGlUSS 0zUqZ8wFgsyKcKJtAamJXnOAKPAs8+vokS0EstOYljxnDaus+xZHgjJt6SSTv7c2uZX4 Y92g== X-Received: by 10.66.135.18 with SMTP id po18mr11972345pab.1.1371738996303; Thu, 20 Jun 2013 07:36:36 -0700 (PDT) Received: from Blade1-02.Blade1-02 ([162.105.146.101]) by mx.google.com with ESMTPSA id vu5sm1066460pab.10.2013.06.20.07.36.32 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Jun 2013 07:36:34 -0700 (PDT) From: Arthur Chunqi Li To: kvm@vger.kernel.org Cc: gleb@redhat.com, pbonzini@redhat.com, jan.kiszka@web.de, Arthur Chunqi Li Subject: [PATCH v4 3/3] kvm-unit-tests: Change two cases to use trap_emulator Date: Thu, 20 Jun 2013 22:36:09 +0800 Message-Id: <1371738969-26658-3-git-send-email-yzt356@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371738969-26658-1-git-send-email-yzt356@gmail.com> References: <1371738969-26658-1-git-send-email-yzt356@gmail.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change two functions (test_mmx_movq_mf and test_movabs) using unified trap_emulator. Signed-off-by: Arthur Chunqi Li --- x86/emulator.c | 70 ++++++++++++-------------------------------------------- 1 file changed, 15 insertions(+), 55 deletions(-) diff --git a/x86/emulator.c b/x86/emulator.c index 876ee5a..68d2b93 100644 --- a/x86/emulator.c +++ b/x86/emulator.c @@ -789,38 +789,20 @@ static void advance_rip_by_3_and_note_exception(struct ex_regs *regs) static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, uint8_t *alt_insn_page, void *insn_ram) { - uint16_t fcw = 0; // all exceptions unmasked - ulong *cr3 = (ulong *)read_cr3(); - - write_cr0(read_cr0() & ~6); // TS, EM - // Place a trapping instruction in the page to trigger a VMEXIT - insn_page[0] = 0x89; // mov %eax, (%rax) - insn_page[1] = 0x00; - insn_page[2] = 0x90; // nop - insn_page[3] = 0xc3; // ret - // Place the instruction we want the hypervisor to see in the alternate page - alt_insn_page[0] = 0x0f; // movq %mm0, (%rax) - alt_insn_page[1] = 0x7f; - alt_insn_page[2] = 0x00; - alt_insn_page[3] = 0xc3; // ret + uint16_t fcw = 0; /* all exceptions unmasked */ + /* movq %mm0, (%rax) */ + void *stack = alloc_page(); + write_cr0(read_cr0() & ~6); /* TS, EM */ exceptions = 0; handle_exception(MF_VECTOR, advance_rip_by_3_and_note_exception); - - // Load the code TLB with insn_page, but point the page tables at - // alt_insn_page (and keep the data TLB clear, for AMD decode assist). - // This will make the CPU trap on the insn_page instruction but the - // hypervisor will see alt_insn_page. - install_page(cr3, virt_to_phys(insn_page), insn_ram); asm volatile("fninit; fldcw %0" : : "m"(fcw)); - asm volatile("fldz; fldz; fdivp"); // generate exception - invlpg(insn_ram); - // Load code TLB - asm volatile("call *%0" : : "r"(insn_ram + 3)); - install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); - // Trap, let hypervisor emulate at alt_insn_page - asm volatile("call *%0" : : "r"(insn_ram), "a"(mem)); - // exit MMX mode + asm volatile("fldz; fldz; fdivp"); /* generate exception */ + + MK_INSN(mmx_movq_mf, "movq %mm0, (%rax) \n\t"); + inregs = (struct regs){ .rsp=(u64)stack+1024 }; + trap_emulator(mem, alt_insn_page, &insn_mmx_movq_mf); + /* exit MMX mode */ asm volatile("fnclex; emms"); report("movq mmx generates #MF", exceptions == 1); handle_exception(MF_VECTOR, 0); @@ -829,33 +811,11 @@ static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, static void test_movabs(uint64_t *mem, uint8_t *insn_page, uint8_t *alt_insn_page, void *insn_ram) { - uint64_t val = 0; - ulong *cr3 = (ulong *)read_cr3(); - - // Pad with RET instructions - memset(insn_page, 0xc3, 4096); - memset(alt_insn_page, 0xc3, 4096); - // Place a trapping instruction in the page to trigger a VMEXIT - insn_page[0] = 0x89; // mov %eax, (%rax) - insn_page[1] = 0x00; - // Place the instruction we want the hypervisor to see in the alternate - // page. A buggy hypervisor will fetch a 32-bit immediate and return - // 0xffffffffc3c3c3c3. - alt_insn_page[0] = 0x48; // mov $0xc3c3c3c3c3c3c3c3, %rcx - alt_insn_page[1] = 0xb9; - - // Load the code TLB with insn_page, but point the page tables at - // alt_insn_page (and keep the data TLB clear, for AMD decode assist). - // This will make the CPU trap on the insn_page instruction but the - // hypervisor will see alt_insn_page. - install_page(cr3, virt_to_phys(insn_page), insn_ram); - // Load code TLB - invlpg(insn_ram); - asm volatile("call *%0" : : "r"(insn_ram + 3)); - // Trap, let hypervisor emulate at alt_insn_page - install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); - asm volatile("call *%1" : "=c"(val) : "r"(insn_ram), "a"(mem), "c"(0)); - report("64-bit mov imm", val == 0xc3c3c3c3c3c3c3c3); + /* mov $0x9090909090909090, %rcx */ + MK_INSN(movabs, "mov $0x9090909090909090, %rcx\n\t"); + inregs = (struct regs){ 0 }; + trap_emulator(mem, alt_insn_page, &insn_movabs); + report("64-bit mov imm2", outregs.rcx == 0x9090909090909090); } static void test_crosspage_mmio(volatile uint8_t *mem)