From patchwork Sun Jul 7 15:13:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arthur Chunqi Li X-Patchwork-Id: 2824583 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F1DA2C0AB2 for ; Sun, 7 Jul 2013 15:13:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C46112012E for ; Sun, 7 Jul 2013 15:13:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CCE9B20122 for ; Sun, 7 Jul 2013 15:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752341Ab3GGPNx (ORCPT ); Sun, 7 Jul 2013 11:13:53 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:53544 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751547Ab3GGPNw (ORCPT ); Sun, 7 Jul 2013 11:13:52 -0400 Received: by mail-pb0-f45.google.com with SMTP id mc8so3471640pbc.4 for ; Sun, 07 Jul 2013 08:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=WFmFed1JVNU5635/IHkPjEEWoPFqtrub3ooH763NXSE=; b=p3bnD/iZh1S+p7Xtm5ggtgF1zVe2ai1yfn/GmhwoJlY3qejCILFPdaHf/uPSYngcHB Guboiu3kzzc0rvz9NaNbEF8GSblzU7NjNkIyhHG5PUT4jbTn9xZ7VEOFODKrjYf81Il9 ea7e8UQQ3vp7JYMfZQ+GbXZyLF1vyqvGOM5EF3pynnheyVVqSvPrh33WurZFD3nd7hI7 UlJCY4ZYHjU0VQ6m3C4E48tU0/3QiXJ+0MsUZSsH9esPXEuxtHcb6Zmqj7K/4tg0IWcl mx8298ft5MFrP52qFujnSGKg5ra5gy02NClkgUdjqhiuZmxovNJbeNaxcFo09rUVhW+Y 6UXg== X-Received: by 10.68.27.105 with SMTP id s9mr17682237pbg.29.1373210032350; Sun, 07 Jul 2013 08:13:52 -0700 (PDT) Received: from Blade1-02.Blade1-02 ([162.105.146.101]) by mx.google.com with ESMTPSA id jf4sm17535393pbb.19.2013.07.07.08.13.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 07 Jul 2013 08:13:51 -0700 (PDT) From: Arthur Chunqi Li To: kvm@vger.kernel.org, qemu-devel@nongnu.org Cc: gleb@redhat.com, pbonzini@redhat.com, jan.kiszka@web.de, nyh@il.ibm.com, Arthur Chunqi Li Subject: [[Qemu-devel] [PATCH]] nVMX: Initialize IA32_FEATURE_CONTROL MSR in reset and migration Date: Sun, 7 Jul 2013 23:13:37 +0800 Message-Id: <1373210017-5103-1-git-send-email-yzt356@gmail.com> X-Mailer: git-send-email 1.7.9.5 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs to clear this MSR when reset vCPU and keep the value of it when migration. This patch add this feature. Signed-off-by: Arthur Chunqi Li --- target-i386/cpu.h | 2 ++ target-i386/kvm.c | 4 ++++ target-i386/machine.c | 22 ++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62e3547..a418e17 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -301,6 +301,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -813,6 +814,7 @@ typedef struct CPUX86State { uint64_t mcg_status; uint64_t msr_ia32_misc_enable; + uint64_t msr_ia32_feature_control; /* exception/interrupt handling */ int error_code; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 39f4fbb..3cb2161 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1122,6 +1122,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (hyperv_vapic_recommended()) { kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0); } + kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->msr_ia32_feature_control); } if (env->mcg_cap) { int i; @@ -1346,6 +1347,7 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_misc_enable) { msrs[n++].index = MSR_IA32_MISC_ENABLE; } + msrs[n++].index = MSR_IA32_FEATURE_CONTROL; if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1444,6 +1446,8 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_MISC_ENABLE: env->msr_ia32_misc_enable = msrs[i].data; break; + case MSR_IA32_FEATURE_CONTROL: + env->msr_ia32_feature_control = msrs[i].data; default: if (msrs[i].index >= MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target-i386/machine.c b/target-i386/machine.c index 3659db9..94ca914 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -399,6 +399,14 @@ static bool misc_enable_needed(void *opaque) return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; } +static bool feature_control_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->msr_ia32_feature_control != 0; +} + static const VMStateDescription vmstate_msr_ia32_misc_enable = { .name = "cpu/msr_ia32_misc_enable", .version_id = 1, @@ -410,6 +418,17 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = { } }; +static const VMStateDescription vmstate_msr_ia32_feature_control = { + .name = "cpu/msr_ia32_feature_control", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -535,6 +554,9 @@ const VMStateDescription vmstate_x86_cpu = { }, { .vmsd = &vmstate_msr_ia32_misc_enable, .needed = misc_enable_needed, + }, { + .vmsd = &vmstate_msr_ia32_feature_control, + .needed = feature_control_needed, } , { /* empty */ }