From patchwork Tue Aug 5 10:39:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 4677101 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C2B5F9F37E for ; Tue, 5 Aug 2014 10:40:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8FB5020166 for ; Tue, 5 Aug 2014 10:40:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53A8B2015A for ; Tue, 5 Aug 2014 10:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753378AbaHEKkI (ORCPT ); Tue, 5 Aug 2014 06:40:08 -0400 Received: from mail-bl2lp0208.outbound.protection.outlook.com ([207.46.163.208]:28092 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753417AbaHEKkE (ORCPT ); Tue, 5 Aug 2014 06:40:04 -0400 Received: from BY2PR03CA065.namprd03.prod.outlook.com (10.141.249.38) by BY2PR03MB505.namprd03.prod.outlook.com (10.141.143.12) with Microsoft SMTP Server (TLS) id 15.0.995.14; Tue, 5 Aug 2014 10:39:48 +0000 Received: from BN1AFFO11FD014.protection.gbl (2a01:111:f400:7c10::158) by BY2PR03CA065.outlook.office365.com (2a01:111:e400:2c5d::38) with Microsoft SMTP Server (TLS) id 15.0.995.14 via Frontend Transport; Tue, 5 Aug 2014 10:39:48 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD014.mail.protection.outlook.com (10.58.52.74) with Microsoft SMTP Server (TLS) id 15.0.990.10 via Frontend Transport; Tue, 5 Aug 2014 10:39:48 +0000 Received: from fsr-fed1764-012.ea.freescale.net (fsr-fed1764-012-010171073213.ea.freescale.net [10.171.73.213]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s75Adfaj018566; Tue, 5 Aug 2014 03:39:46 -0700 From: Mihai Caraman To: CC: , Mihai Caraman Subject: [PATCH v3 4/5] KVM: PPC: Booke: Add ONE_REG IVORs support Date: Tue, 5 Aug 2014 13:39:34 +0300 Message-ID: <1407235175-30994-5-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1407235175-30994-1-git-send-email-mihai.caraman@freescale.com> References: <1407235175-30994-1-git-send-email-mihai.caraman@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(33646002)(88136002)(87936001)(44976005)(104016003)(83322001)(19580405001)(19580395003)(76482001)(87286001)(85852003)(83072002)(92726001)(92566001)(6806004)(89996001)(81342001)(106466001)(81542001)(77982001)(46102001)(105606002)(74662001)(50466002)(95666004)(85306004)(48376002)(79102001)(21056001)(74502001)(97736001)(36756003)(77156001)(80022001)(4396001)(50226001)(47776003)(64706001)(20776003)(99396002)(229853001)(2351001)(62966002)(76176999)(84676001)(50986999)(107046002)(104166001)(110136001)(93916002)(26826002)(86362001)(31966008)(68736004)(102836001); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB505; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 02945962BD Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=mihai.caraman@freescale.com; X-OriginatorOrg: freescale.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common. Signed-off-by: Mihai Caraman --- v3: - new patch arch/powerpc/include/uapi/asm/kvm.h | 24 +++++++ arch/powerpc/kvm/booke.c | 132 ++++++++++++++++++++++++++++++++++++ arch/powerpc/kvm/e500.c | 42 +++++++++++- arch/powerpc/kvm/e500mc.c | 32 +++++++++ 4 files changed, 228 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h index 7a27ff0..174fed0 100644 --- a/arch/powerpc/include/uapi/asm/kvm.h +++ b/arch/powerpc/include/uapi/asm/kvm.h @@ -563,6 +563,30 @@ struct kvm_get_htab_header { #define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9) #define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba) +/* Booke IVOR registers */ +#define KVM_REG_PPC_IVOR0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc0) +#define KVM_REG_PPC_IVOR1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc1) +#define KVM_REG_PPC_IVOR2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc2) +#define KVM_REG_PPC_IVOR3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc3) +#define KVM_REG_PPC_IVOR4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc4) +#define KVM_REG_PPC_IVOR5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc5) +#define KVM_REG_PPC_IVOR6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc6) +#define KVM_REG_PPC_IVOR7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc7) +#define KVM_REG_PPC_IVOR8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc8) +#define KVM_REG_PPC_IVOR9 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc9) +#define KVM_REG_PPC_IVOR10 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xca) +#define KVM_REG_PPC_IVOR11 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcb) +#define KVM_REG_PPC_IVOR12 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcc) +#define KVM_REG_PPC_IVOR13 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcd) +#define KVM_REG_PPC_IVOR14 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xce) +#define KVM_REG_PPC_IVOR15 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcf) +#define KVM_REG_PPC_IVOR32 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd0) +#define KVM_REG_PPC_IVOR33 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd1) +#define KVM_REG_PPC_IVOR34 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd2) +#define KVM_REG_PPC_IVOR35 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd3) +#define KVM_REG_PPC_IVOR36 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd4) +#define KVM_REG_PPC_IVOR37 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd5) + /* Transactional Memory checkpointed state: * This is all GPRs, all VSX regs and a subset of SPRs */ diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 4fe7f68..ffa82a5 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -1565,6 +1565,72 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, int r = 0; switch (id) { + case KVM_REG_PPC_IVOR0: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]); + break; + case KVM_REG_PPC_IVOR1: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]); + break; + case KVM_REG_PPC_IVOR2: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]); + break; + case KVM_REG_PPC_IVOR3: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]); + break; + case KVM_REG_PPC_IVOR4: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]); + break; + case KVM_REG_PPC_IVOR5: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]); + break; + case KVM_REG_PPC_IVOR6: + *val = get_reg_val(id, vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]); + break; + case KVM_REG_PPC_IVOR7: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]); + break; + case KVM_REG_PPC_IVOR8: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]); + break; + case KVM_REG_PPC_IVOR9: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]); + break; + case KVM_REG_PPC_IVOR10: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]); + break; + case KVM_REG_PPC_IVOR11: + *val = get_reg_val(id, vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]); + break; + case KVM_REG_PPC_IVOR12: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]); + break; + case KVM_REG_PPC_IVOR13: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]); + break; + case KVM_REG_PPC_IVOR14: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]); + break; + case KVM_REG_PPC_IVOR15: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]); + break; + case KVM_REG_PPC_IVOR35: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR]); + break; case KVM_REG_PPC_IAC1: *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1); break; @@ -1621,6 +1687,72 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, int r = 0; switch (id) { + case KVM_REG_PPC_IVOR0: + vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR1: + vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR2: + vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR3: + vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR4: + vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR5: + vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR6: + vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR7: + vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR8: + vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR9: + vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR10: + vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR11: + vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR12: + vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR13: + vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR14: + vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR15: + vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR35: + vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR] = + set_reg_val(id, *val); + break; case KVM_REG_PPC_IAC1: vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val); break; diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c index 2e02ed8..08f61bf 100644 --- a/arch/powerpc/kvm/e500.c +++ b/arch/powerpc/kvm/e500.c @@ -433,14 +433,52 @@ static int kvmppc_core_set_sregs_e500(struct kvm_vcpu *vcpu, static int kvmppc_get_one_reg_e500(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) { - int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); + int r = 0; + + switch (id) { + case KVM_REG_PPC_IVOR32: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL]); + break; + case KVM_REG_PPC_IVOR33: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA]); + break; + case KVM_REG_PPC_IVOR34: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND]); + break; + default: + r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); + break; + } + return r; } static int kvmppc_set_one_reg_e500(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) { - int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); + int r = 0; + + switch (id) { + case KVM_REG_PPC_IVOR32: + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR33: + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR34: + vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND] = + set_reg_val(id, *val); + break; + default: + r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); + break; + } + return r; } diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index 67c06eb..19dd927 100644 --- a/arch/powerpc/kvm/e500mc.c +++ b/arch/powerpc/kvm/e500mc.c @@ -268,6 +268,22 @@ static int kvmppc_get_one_reg_e500mc(struct kvm_vcpu *vcpu, u64 id, int r = 0; switch (id) { + case KVM_REG_PPC_IVOR32: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL]); + break; + case KVM_REG_PPC_IVOR33: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST]); + break; + case KVM_REG_PPC_IVOR36: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL]); + break; + case KVM_REG_PPC_IVOR37: + *val = get_reg_val(id, + vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT]); + break; case KVM_REG_PPC_SPRG9: *val = get_reg_val(id, vcpu->arch.sprg9); break; @@ -284,6 +300,22 @@ static int kvmppc_set_one_reg_e500mc(struct kvm_vcpu *vcpu, u64 id, int r = 0; switch (id) { + case KVM_REG_PPC_IVOR32: + vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR33: + vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR36: + vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL] = + set_reg_val(id, *val); + break; + case KVM_REG_PPC_IVOR37: + vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT] = + set_reg_val(id, *val); + break; case KVM_REG_PPC_SPRG9: vcpu->arch.sprg9 = set_reg_val(id, *val); break;