From patchwork Tue Sep 16 12:22:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nadav Amit X-Patchwork-Id: 4917701 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 170D5BEEA5 for ; Tue, 16 Sep 2014 12:23:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05E22201ED for ; Tue, 16 Sep 2014 12:23:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8955120220 for ; Tue, 16 Sep 2014 12:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753421AbaIPMWz (ORCPT ); Tue, 16 Sep 2014 08:22:55 -0400 Received: from mailgw12.technion.ac.il ([132.68.225.12]:63213 "EHLO mailgw12.technion.ac.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753206AbaIPMWx (ORCPT ); Tue, 16 Sep 2014 08:22:53 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AiYFALwqGFSERCAB/2dsb2JhbABggw2BKtJlAYEUFgEBeIQEAQUnUhBRVwcSiD61LIYqGI9LB4RLBYYfhRqnFYNhaYJKAQEB X-IPAS-Result: AiYFALwqGFSERCAB/2dsb2JhbABggw2BKtJlAYEUFgEBeIQEAQUnUhBRVwcSiD61LIYqGI9LB4RLBYYfhRqnFYNhaYJKAQEB X-IronPort-AV: E=Sophos;i="5.04,534,1406581200"; d="scan'208";a="122507356" Received: from csa.cs.technion.ac.il ([132.68.32.1]) by mailgw12.technion.ac.il with ESMTP; 16 Sep 2014 15:22:49 +0300 Received: from csn.cs.technion.ac.il (csn.cs.technion.ac.il [132.68.32.15]) by csa.cs.technion.ac.il (Postfix) with ESMTP id F25E8140039; Tue, 16 Sep 2014 15:22:48 +0300 (IDT) Received: from csl-tapuz20.cs.technion.ac.il (csl-tapuz20.cs.technion.ac.il [132.68.206.58]) by csn.cs.technion.ac.il (Postfix) with ESMTPSA id E6FFDA1B9B; Tue, 16 Sep 2014 15:22:48 +0300 (IDT) From: Nadav Amit To: pbonzini@redhat.com, hpa@zytor.com, mingo@redhat.com, tglx@linutronix.de Cc: x86@kernel.org, kvm@vger.kernel.org, nadav.amit@gmail.com, Nadav Amit Subject: [PATCH 2/3] x86: Use new cpuid structs in cpuid functions Date: Tue, 16 Sep 2014 15:22:39 +0300 Message-Id: <1410870160-28845-3-git-send-email-namit@cs.technion.ac.il> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1410870160-28845-1-git-send-email-namit@cs.technion.ac.il> References: <1410870160-28845-1-git-send-email-namit@cs.technion.ac.il> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current code that decodes cpuid fields is somewhat cryptic, since it uses many bit operations. Using cpuid structs instead for clarifying the code. Introducing no functional change. Signed-off-by: Nadav Amit --- arch/x86/kernel/cpu/common.c | 56 +++++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e4ab2b4..b57c160 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -41,6 +41,7 @@ #include #include #include +#include #ifdef CONFIG_X86_LOCAL_APIC #include @@ -444,13 +445,17 @@ static void get_model_name(struct cpuinfo_x86 *c) void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) { - unsigned int n, dummy, ebx, ecx, edx, l2size; + unsigned int n, dummy, dummy2, l2size; + union cpuid8_5_ecx_edx ecx5, edx5; + union cpuid8_6_ebx ebx6; + union cpuid8_6_ecx ecx6; n = c->extended_cpuid_level; if (n >= 0x80000005) { - cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); - c->x86_cache_size = (ecx>>24) + (edx>>24); + cpuid(0x80000005, &dummy, &dummy2, &ecx5.full, &edx5.full); + c->x86_cache_size = ecx5.split.cache_size + + edx5.split.cache_size; #ifdef CONFIG_X86_64 /* On K8 L1 TLB is inclusive, so don't count it */ c->x86_tlbsize = 0; @@ -460,11 +465,11 @@ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) if (n < 0x80000006) /* Some chips just has a large L1. */ return; - cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); - l2size = ecx >> 16; + cpuid(0x80000006, &dummy, &ebx6.full, &ecx6.full, &dummy2); + l2size = ecx6.split.cache_size; #ifdef CONFIG_X86_64 - c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); + c->x86_tlbsize += ebx6.split.dtlb_entries + ebx6.split.itlb_entries; #else /* do processor-specific cache resizing */ if (this_cpu->legacy_cache_size) @@ -505,9 +510,10 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c) void detect_ht(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_HT - u32 eax, ebx, ecx, edx; + u32 eax, ecx, edx; int index_msb, core_bits; static bool printed; + union cpuid1_ebx ebx; if (!cpu_has(c, X86_FEATURE_HT)) return; @@ -518,9 +524,9 @@ void detect_ht(struct cpuinfo_x86 *c) if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) return; - cpuid(1, &eax, &ebx, &ecx, &edx); + cpuid(1, &eax, &ebx.full, &ecx, &edx); - smp_num_siblings = (ebx & 0xff0000) >> 16; + smp_num_siblings = ebx.split.max_logical_proc; if (smp_num_siblings == 1) { printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); @@ -591,20 +597,22 @@ void cpu_detect(struct cpuinfo_x86 *c) c->x86 = 4; /* Intel-defined flags: level 0x00000001 */ if (c->cpuid_level >= 0x00000001) { - u32 junk, tfms, cap0, misc; + u32 junk, cap0; + union cpuid1_eax tfms; + union cpuid1_ebx misc; - cpuid(0x00000001, &tfms, &misc, &junk, &cap0); - c->x86 = (tfms >> 8) & 0xf; - c->x86_model = (tfms >> 4) & 0xf; - c->x86_mask = tfms & 0xf; + cpuid(0x00000001, &tfms.full, &misc.full, &junk, &cap0); + c->x86 = tfms.split.family_id; + c->x86_model = tfms.split.model; + c->x86_mask = tfms.split.stepping_id; if (c->x86 == 0xf) - c->x86 += (tfms >> 20) & 0xff; + c->x86 += tfms.split.extended_family_id; if (c->x86 >= 0x6) - c->x86_model += ((tfms >> 16) & 0xf) << 4; + c->x86_model += tfms.split.extended_model_id << 4; - if (cap0 & (1<<19)) { - c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; + if (cap0 & (1 << (X86_FEATURE_CLFLUSH & 31))) { + c->x86_clflush_size = misc.split.clflush_size * 8; c->x86_cache_alignment = c->x86_clflush_size; } } @@ -654,10 +662,11 @@ void get_cpu_cap(struct cpuinfo_x86 *c) } if (c->extended_cpuid_level >= 0x80000008) { - u32 eax = cpuid_eax(0x80000008); + union cpuid_8_8_eax eax; - c->x86_virt_bits = (eax >> 8) & 0xff; - c->x86_phys_bits = eax & 0xff; + eax.full = cpuid_eax(0x80000008); + c->x86_virt_bits = eax.split.virt_as; + c->x86_phys_bits = eax.split.phys_as; } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) @@ -814,7 +823,10 @@ static void generic_identify(struct cpuinfo_x86 *c) get_cpu_cap(c); if (c->cpuid_level >= 0x00000001) { - c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; + union cpuid1_ebx ebx; + + ebx.full = cpuid_ebx(1); + c->initial_apicid = ebx.split.initial_apicid; #ifdef CONFIG_X86_32 # ifdef CONFIG_X86_HT c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);