From patchwork Fri Jul 3 11:26:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 6714311 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 732E0C05AC for ; Fri, 3 Jul 2015 11:27:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77FEB2066C for ; Fri, 3 Jul 2015 11:27:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6F4B42066B for ; Fri, 3 Jul 2015 11:27:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755305AbbGCL1H (ORCPT ); Fri, 3 Jul 2015 07:27:07 -0400 Received: from foss.arm.com ([217.140.101.70]:52872 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754756AbbGCL1A (ORCPT ); Fri, 3 Jul 2015 07:27:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52E2A601; Fri, 3 Jul 2015 04:27:30 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.203.153]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2A0033F5BF; Fri, 3 Jul 2015 04:26:58 -0700 (PDT) From: Andre Przywara To: will.deacon@arm.com, marc.zyngier@arm.com Cc: penberg@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 09/10] arm: add support for supplying GICv3 redistributor addresses Date: Fri, 3 Jul 2015 12:26:37 +0100 Message-Id: <1435922798-14375-10-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.3.5 In-Reply-To: <1435922798-14375-1-git-send-email-andre.przywara@arm.com> References: <1435922798-14375-1-git-send-email-andre.przywara@arm.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of the GIC virtual CPU interface an emulated GICv3 needs to have accesses to its emulated redistributors trapped in the guest. Add code to tell the kernel about the mapping if a GICv3 emulation was requested by the user. This contains some defines which are not (yet) in the (32 bit) header files to allow compilation for ARM. Signed-off-by: Andre Przywara Reviewed-by: Marc Zyngier --- arm/gic.c | 36 +++++++++++++++++++++++++++++++++++- arm/include/arm-common/gic.h | 1 + arm/include/arm-common/kvm-arch.h | 7 +++++++ 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/arm/gic.c b/arm/gic.c index b6c5868..efe4b42 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -9,7 +9,18 @@ #include #include +/* Those names are not defined for ARM (yet) */ +#ifndef KVM_VGIC_V3_ADDR_TYPE_DIST +#define KVM_VGIC_V3_ADDR_TYPE_DIST 2 +#endif + +#ifndef KVM_VGIC_V3_ADDR_TYPE_REDIST +#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 +#endif + static int gic_fd = -1; +static u64 gic_redists_base; +static u64 gic_redists_size; static int gic__create_device(struct kvm *kvm, enum irqchip_type type) { @@ -28,12 +39,21 @@ static int gic__create_device(struct kvm *kvm, enum irqchip_type type) .group = KVM_DEV_ARM_VGIC_GRP_ADDR, .addr = (u64)(unsigned long)&dist_addr, }; + struct kvm_device_attr redist_attr = { + .group = KVM_DEV_ARM_VGIC_GRP_ADDR, + .attr = KVM_VGIC_V3_ADDR_TYPE_REDIST, + .addr = (u64)(unsigned long)&gic_redists_base, + }; switch (type) { case IRQCHIP_GICV2: gic_device.type = KVM_DEV_TYPE_ARM_VGIC_V2; dist_attr.attr = KVM_VGIC_V2_ADDR_TYPE_DIST; break; + case IRQCHIP_GICV3: + gic_device.type = KVM_DEV_TYPE_ARM_VGIC_V3; + dist_attr.attr = KVM_VGIC_V3_ADDR_TYPE_DIST; + break; } err = ioctl(kvm->vm_fd, KVM_CREATE_DEVICE, &gic_device); @@ -46,6 +66,9 @@ static int gic__create_device(struct kvm *kvm, enum irqchip_type type) case IRQCHIP_GICV2: err = ioctl(gic_fd, KVM_SET_DEVICE_ATTR, &cpu_if_attr); break; + case IRQCHIP_GICV3: + err = ioctl(gic_fd, KVM_SET_DEVICE_ATTR, &redist_attr); + break; } if (err) goto out_err; @@ -97,6 +120,10 @@ int gic__create(struct kvm *kvm, enum irqchip_type type) switch (type) { case IRQCHIP_GICV2: break; + case IRQCHIP_GICV3: + gic_redists_size = kvm->cfg.nrcpus * ARM_GIC_REDIST_SIZE; + gic_redists_base = ARM_GIC_DIST_BASE - gic_redists_size; + break; default: return -ENODEV; } @@ -156,12 +183,19 @@ void gic__generate_fdt_nodes(void *fdt, u32 phandle, enum irqchip_type type) const char *compatible; u64 reg_prop[] = { cpu_to_fdt64(ARM_GIC_DIST_BASE), cpu_to_fdt64(ARM_GIC_DIST_SIZE), - cpu_to_fdt64(ARM_GIC_CPUI_BASE), cpu_to_fdt64(ARM_GIC_CPUI_SIZE), + 0, 0, /* to be filled */ }; switch (type) { case IRQCHIP_GICV2: compatible = "arm,cortex-a15-gic"; + reg_prop[2] = cpu_to_fdt64(ARM_GIC_CPUI_BASE); + reg_prop[3] = cpu_to_fdt64(ARM_GIC_CPUI_SIZE); + break; + case IRQCHIP_GICV3: + compatible = "arm,gic-v3"; + reg_prop[2] = cpu_to_fdt64(gic_redists_base); + reg_prop[3] = cpu_to_fdt64(gic_redists_size); break; default: return; diff --git a/arm/include/arm-common/gic.h b/arm/include/arm-common/gic.h index d524f55..4fde5ac 100644 --- a/arm/include/arm-common/gic.h +++ b/arm/include/arm-common/gic.h @@ -23,6 +23,7 @@ enum irqchip_type { IRQCHIP_GICV2, + IRQCHIP_GICV3, }; struct kvm; diff --git a/arm/include/arm-common/kvm-arch.h b/arm/include/arm-common/kvm-arch.h index 90d6733..0f5fb7f 100644 --- a/arm/include/arm-common/kvm-arch.h +++ b/arm/include/arm-common/kvm-arch.h @@ -30,6 +30,13 @@ #define KVM_PCI_MMIO_AREA (KVM_PCI_CFG_AREA + ARM_PCI_CFG_SIZE) #define KVM_VIRTIO_MMIO_AREA ARM_MMIO_AREA +/* + * On a GICv3 there must be one redistributor per vCPU. + * The value here is the size for one, we multiply this at runtime with + * the number of requested vCPUs to get the actual size. + */ +#define ARM_GIC_REDIST_SIZE 0x20000 + #define KVM_IRQ_OFFSET GIC_SPI_IRQ_BASE #define KVM_VM_TYPE 0