From patchwork Mon Jul 6 02:17:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 6719231 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A381C9F38C for ; Mon, 6 Jul 2015 02:18:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A0A8420642 for ; Mon, 6 Jul 2015 02:18:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 936A52049C for ; Mon, 6 Jul 2015 02:18:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753595AbbGFCSl (ORCPT ); Sun, 5 Jul 2015 22:18:41 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:34815 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753608AbbGFCSj (ORCPT ); Sun, 5 Jul 2015 22:18:39 -0400 Received: by pdbep18 with SMTP id ep18so96544156pdb.1 for ; Sun, 05 Jul 2015 19:18:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Qxz7wltVlOeNYf+fU5zFWDmnMPTTzUSI62n3RGd3vf0=; b=acz/EKNdY7VyiNe99iD2F4vs3u4IKLUY0TiwjEun/xz4Ms1NtwlAAzVi81aV3Nu09k aqOpZl5scMoLvU3R6TnovZlRJYwt8heQRat5aZMA+arIZs3ZaGzQ7XWODA4+O+Yuizgc 8f7TYEi6BpZtAOFhEp7TArBlZKujGPhGxcfzxd3ObpfOw1XWPb+1lwH0uGPOhS48BROH K0kzd5Bh3ipl4eF51BO4hjftgl6OUiw/o/ORjVmMITGDtyEkukyTKmuEN3+yhQPPZpds qKeyYUeT+mo05qDfDbSFVvQw7kHgLRQc4N+7+4sYfrQBQDmPmBDyfRrliQJfTUUkX++h 91Lg== X-Gm-Message-State: ALoCoQlNM0JuxXERUzEleZbr9+uXrSX+Ca5vAEMmRzKzb53KT1+inAAfhCBgnqXKVSKnW8IuyRem X-Received: by 10.70.130.79 with SMTP id oc15mr18281287pdb.55.1436149119195; Sun, 05 Jul 2015 19:18:39 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id hl6sm9582209pdb.28.2015.07.05.19.18.37 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:18:38 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, christoffer.dall@linaro.org, will.deacon@arm.com, marc.zyngier@arm.com, alex.bennee@linaro.org, shannon.zhao@linaro.org, zhaoshenglong@huawei.com Subject: [PATCH 09/18] KVM: ARM64: Add reset and access handlers for PMXEVCNTR_EL0 register Date: Mon, 6 Jul 2015 10:17:39 +0800 Message-Id: <1436149068-3784-10-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shannon Zhao Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When reading PMXEVCNTR_EL0, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 21 ++++++++++++++++++++- include/kvm/arm_pmu.h | 11 +++++++++++ virt/kvm/arm/pmu.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b4f8dd9..2bcf1a0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -356,6 +356,25 @@ static bool access_pmxevtyper(struct kvm_vcpu *vcpu, return true; } +static bool access_pmxevcntr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + unsigned long val; + + if (p->is_write) { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_set_counter_value(vcpu, vcpu_sys_reg(vcpu, PMSELR_EL0), + val & 0xffffffffUL); + } else { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_sys_reg(vcpu, PMSELR_EL0)); + *vcpu_reg(vcpu, p->Rt) = val; + } + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -577,7 +596,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmxevtyper, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), - trap_raz_wi }, + access_pmxevcntr, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), trap_raz_wi }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 1050b24..40ab4a0 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -45,11 +45,22 @@ struct kvm_pmu { #ifdef CONFIG_KVM_ARM_PMU void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val); +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx); void kvm_pmu_init(struct kvm_vcpu *vcpu); #else static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val) {} +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx) +{ + return 0; +} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx) {} static inline void kvm_pmu_init(struct kvm_vcpu *vcpu) {} diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 50a3c82..361fa51 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -97,6 +97,43 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) } /** + * kvm_pmu_set_counter_value - set PMU counter value + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * @val: the value to be set + */ +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc = &pmu->pmc[select_idx]; + + pmc->counter = val; +} + +/** + * kvm_pmu_set_counter_value - set PMU counter value + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * + * Call perf_event API to get the event count + */ +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx) +{ + u64 enabled, running; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc = &pmu->pmc[select_idx]; + unsigned long counter = pmc->counter; + + if (pmc->perf_event) { + counter += perf_event_read_value(pmc->perf_event, + &enabled, &running); + } + return counter; +} + +/** * kvm_pmu_find_hw_event - find hardware event * @pmu: The pmu pointer * @event_select: The number of selected event type