From patchwork Mon Jul 6 02:17:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 6719271 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A06E49F38C for ; Mon, 6 Jul 2015 02:19:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B430420652 for ; Mon, 6 Jul 2015 02:19:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF48B20642 for ; Mon, 6 Jul 2015 02:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753642AbbGFCTA (ORCPT ); Sun, 5 Jul 2015 22:19:00 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:33651 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753611AbbGFCS6 (ORCPT ); Sun, 5 Jul 2015 22:18:58 -0400 Received: by pdbdz6 with SMTP id dz6so1064511pdb.0 for ; Sun, 05 Jul 2015 19:18:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a8M3p9WMgfzRmneLF9JLbb7bEjlbvrDPmk3v9AAlSqg=; b=WON+D5Y83/i/zPw13uGUCLxuqanDR5iAyFoR3KkrvIenO5fwoQULT+k4yJW/ETum4j 55XpAo6EeHg2642/x48WkNA+T2+ymCy/EHEdwRsCNOjcK0Kg7wos2nAj5fwlqPyuz+dT 4urIAA2p88rmf2g4cSiOemRz2+WHgfmUz7EgtUngZy0ToidL4Y+wCc2hV9CWC6eC87EK 4DcNRfCnWYnQWsHRncqSha4BXI82VU6c7MbYiVTnuvt1zPOnP2u+2OdJ1YO2/SR1BOfU /9ilyyhJ97cpmZOmJZwLMpt3HH2nt0rA4bu47fuDNzItLDJj22hkCRCcX9H1EUKuY1aN c9+Q== X-Gm-Message-State: ALoCoQle42nCcO5Au2L4HR86TP6hmYGHdiRVnvS1oX8Lrvu3oCbSZM782PHifxfKf+SyuZFoLmoX X-Received: by 10.68.229.40 with SMTP id sn8mr98898881pbc.59.1436149138012; Sun, 05 Jul 2015 19:18:58 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id ml6sm16212407pdb.69.2015.07.05.19.18.55 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:18:56 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, christoffer.dall@linaro.org, will.deacon@arm.com, marc.zyngier@arm.com, alex.bennee@linaro.org, shannon.zhao@linaro.org, zhaoshenglong@huawei.com Subject: [PATCH 13/18] KVM: ARM64: Add reset and access handlers for PMOVSSET_EL0 and PMOVSCLR_EL0 register Date: Mon, 6 Jul 2015 10:17:43 +0800 Message-Id: <1436149068-3784-14-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shannon Zhao Since the reset value of PMOVSSET_EL0 and PMOVSCLR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMOVSSET_EL0 or PMOVSCLR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index cbc07b8..ec80937 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -496,6 +496,32 @@ static bool access_pmintenclr(struct kvm_vcpu *vcpu, return true; } +/* PMOVSSET_EL0 accessor. */ +static bool access_pmovsset(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + vcpu->arch.pmu.overflow_status |= *vcpu_reg(vcpu, p->Rt); + else + *vcpu_reg(vcpu, p->Rt) = vcpu->arch.pmu.overflow_status; + + return true; +} + +/* PMOVSCLR_EL0 accessor. */ +static bool access_pmovsclr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + vcpu->arch.pmu.overflow_status &= (~*vcpu_reg(vcpu, p->Rt)); + else + *vcpu_reg(vcpu, p->Rt) = vcpu->arch.pmu.overflow_status; + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -696,7 +722,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmcntenclr, reset_unknown, PMCNTENCLR_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), - trap_raz_wi }, + access_pmovsclr, reset_unknown, PMOVSCLR_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), trap_raz_wi }, @@ -723,7 +749,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { trap_raz_wi }, /* PMOVSSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), - trap_raz_wi }, + access_pmovsset, reset_unknown, PMOVSSET_EL0 }, /* TPIDR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),