From patchwork Wed Jul 29 13:28:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 6893961 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9F61E9F38B for ; Wed, 29 Jul 2015 13:28:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C65812068F for ; Wed, 29 Jul 2015 13:28:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5CF5203F3 for ; Wed, 29 Jul 2015 13:28:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751715AbbG2N2S (ORCPT ); Wed, 29 Jul 2015 09:28:18 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:38239 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750819AbbG2N2S (ORCPT ); Wed, 29 Jul 2015 09:28:18 -0400 Received: by wibxm9 with SMTP id xm9so26473742wib.1 for ; Wed, 29 Jul 2015 06:28:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=4Xlq7gfB9KKrdjgsYbIYC26xJMXqMTzpjQKA3iMTN38=; b=VWCxMMnp8AIwuo5zLb7myrM3AXCNVZloyCVkm4WP32VHuzksERWOFti+CytQ3OXZnK 3GyTPwMwLbpbONaex8+MPzaoenPuUPnJs6y+mKPUiRO9ty2AgVdX5ZVYCX5KSig+w83J 8DJULT0+k64e/ryft6ynCZIwHPXUa4S36DGcqlGX94oWhDpsDkzA+GMqAG6SJig9oDjv o2BPUITz8DBNWJgFIz/B5HmXi0RX5W/UULdLi6Ayt8SEgWkm8RSoUkiK0D3RV9AojG5h N2r5DYVqTyXkr5XGrtgFA25U6xxU+MMVss9mBzJIjgHoee9tQnQxN7e1j8nLgmtL9oCA HUew== X-Received: by 10.180.207.242 with SMTP id lz18mr16802799wic.66.1438176496982; Wed, 29 Jul 2015 06:28:16 -0700 (PDT) Received: from 640k.lan (dynamic-adsl-94-39-188-187.clienti.tiscali.it. [94.39.188.187]) by smtp.gmail.com with ESMTPSA id ho10sm38585075wjb.39.2015.07.29.06.28.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Jul 2015 06:28:15 -0700 (PDT) From: Paolo Bonzini To: kvm@vger.kernel.org Cc: srutherford@google.com Subject: [PATCH kvm-unit-tests] x86: ioapic: add tests around retriggering of level interrupts Date: Wed, 29 Jul 2015 15:28:13 +0200 Message-Id: <1438176493-26033-1-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Test resampling of level interrupts after EOI, by leaving the IRQ line set in the ISR. One tests does reset the IRQ line after a while, the other uses masking instead in the ISR. Signed-off-by: Paolo Bonzini --- x86/ioapic.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/x86/ioapic.c b/x86/ioapic.c index 1fcf67e..d43d5c1 100644 --- a/x86/ioapic.c +++ b/x86/ioapic.c @@ -188,6 +188,31 @@ static void test_ioapic_level_sequential(void) report("sequential level interrupts", g_isr_99 == 2); } +static volatile int g_isr_9a; + +static void ioapic_isr_9a(isr_regs_t *regs) +{ + ++g_isr_9a; + if (g_isr_9a == 2) + set_irq_line(0x0e, 0); + eoi(); +} + +static void test_ioapic_level_retrigger(void) +{ + handle_irq(0x9a, ioapic_isr_9a); + set_ioapic_redir(0x0e, 0x9a, LEVEL_TRIGGERED); + + asm volatile ("cli"); + set_irq_line(0x0e, 1); + while (g_isr_9a != 2) + asm volatile ("sti; hlt; cli"); + + asm volatile ("sti"); + + report("retriggered level interrupts without masking", g_isr_9a == 2); +} + static volatile int g_isr_81; static void ioapic_isr_81(isr_regs_t *regs) @@ -242,6 +267,30 @@ static void test_ioapic_level_mask(void) report("unmasked level interrupt", g_isr_82 == 1); } +static volatile int g_isr_83; + +static void ioapic_isr_83(isr_regs_t *regs) +{ + ++g_isr_83; + set_mask(0x0e, true); + eoi(); +} + +static void test_ioapic_level_retrigger_mask(void) +{ + handle_irq(0x83, ioapic_isr_83); + set_ioapic_redir(0x0e, 0x83, LEVEL_TRIGGERED); + + set_irq_line(0x0e, 1); + asm volatile ("nop"); + set_mask(0x0e, false); + asm volatile ("nop"); + report("retriggered level interrupts with mask", g_isr_83 == 2); + + set_irq_line(0x0e, 0); + set_mask(0x0e, false); +} + int main(void) { @@ -263,9 +312,11 @@ int main(void) test_ioapic_simultaneous(); test_ioapic_level_coalesce(); test_ioapic_level_sequential(); + test_ioapic_level_retrigger(); test_ioapic_edge_mask(); test_ioapic_level_mask(); + test_ioapic_level_retrigger_mask(); return report_summary(); }