From patchwork Sun Aug 30 13:54:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 7097291 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 60EF49F36E for ; Sun, 30 Aug 2015 13:53:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 851AC207BE for ; Sun, 30 Aug 2015 13:53:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9BA9E207BB for ; Sun, 30 Aug 2015 13:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753534AbbH3Nxm (ORCPT ); Sun, 30 Aug 2015 09:53:42 -0400 Received: from mail-lb0-f172.google.com ([209.85.217.172]:34729 "EHLO mail-lb0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753413AbbH3NxX (ORCPT ); Sun, 30 Aug 2015 09:53:23 -0400 Received: by lbbtg9 with SMTP id tg9so48775128lbb.1 for ; Sun, 30 Aug 2015 06:53:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j+1AauztTZV4Ql+i+sg5B2BvYYaD5cY1RaRnZ6GGw1Y=; b=jWki3BiWUELrMKrjXeU87FTiNWsySk8IjjADz6RAjB3zkPkYZl/ZbmStoufvnfjN53 1O2HbSU5GApiCi+IpHG7zHlP+z7EP9WnVERxUa8DNKmmncWtuKjIf6W+K+2dZvNyX5Rp DTJ/3CC0G8Mh5nQ7ULnTmCwYPTeu1jg/LFfchNEovAaL6NE3krClbtPcgaX1vbRBtJoj v2GUONSepjO0rYBNNtaUlLZ+EI0UV6scoaU7bsnuMA63akMPQX16pprazd8VKYLLyZaO gJn2RVhaKCXpf5T2jkDOaZAiqUR/3qbXxJXpiB6QRxznsPFYG5coO77Ov8gpMlxc4QKV qKdw== X-Gm-Message-State: ALoCoQlCglPkmi6irPwZW6bepYgpo+GEskY55mIyHF4rHNks+bitcSJ9B3LGNcmTM3bxXFEuqG3m X-Received: by 10.152.6.41 with SMTP id x9mr6607578lax.120.1440942802350; Sun, 30 Aug 2015 06:53:22 -0700 (PDT) Received: from localhost.localdomain (0187900153.0.fullrate.dk. [2.110.55.193]) by smtp.gmail.com with ESMTPSA id qm6sm3069212lbb.23.2015.08.30.06.53.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 30 Aug 2015 06:53:21 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Christoffer Dall Subject: [PATCH 4/9] arm/arm64: Implement GICD_ICFGR as RO for PPIs Date: Sun, 30 Aug 2015 15:54:21 +0200 Message-Id: <1440942866-23802-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.1.2.330.g565301e.dirty In-Reply-To: <1440942866-23802-1-git-send-email-christoffer.dall@linaro.org> References: <1440942866-23802-1-git-send-email-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier --- virt/kvm/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index c5750be..0ba92d3 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -655,7 +655,7 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { if (offset < 8) { - *reg = ~0U; /* Force PPIs/SGIs to 1 */ + /* Ignore writes to read-only SGI and PPI bits */ return false; }