From patchwork Thu Sep 24 22:31:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 7261251 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B6B159F30C for ; Thu, 24 Sep 2015 22:32:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8D0120B2B for ; Thu, 24 Sep 2015 22:32:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B599A20B29 for ; Thu, 24 Sep 2015 22:32:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932108AbbIXWcd (ORCPT ); Thu, 24 Sep 2015 18:32:33 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:34021 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754037AbbIXWcc (ORCPT ); Thu, 24 Sep 2015 18:32:32 -0400 Received: by padhy16 with SMTP id hy16so85168844pad.1 for ; Thu, 24 Sep 2015 15:32:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nrmXF/ajyZSY84wnTGz5zIc+A4V2fY/u7HAq7uxRkXs=; b=B0GXEGkgDMiYaaWdjwjbWbKwMiwlQ3i2N+6BkkNLgjdNvcJAYnMasa0v9mWFyrdXnj DkKdG5v0i1+8yx45WhkuD0TSRIOeOIp8Jg8U/3OTnstueBb80pDKt7RNw2lxpPG+sCrC jyWMb2zOJNEQdi3NJuBXeEzEnmRyL+aLOQfVFgLe9JL5WKNjq02Grae065oQcqlfZWDY swBRTMVgsNz0uQnJFkHGCx90cKQPYR2vLj9NHy353FjIRf/h4t3Hz4DI7WxNH97g0bSf xChBr7DVemmuwoSd0qyaJzvmjo7AhbtT7UGBBidEWAvfNNasO9QVdf0YFHiIy8DVcCz/ ev6Q== X-Gm-Message-State: ALoCoQnGk+AOQP4f4cnYsSvJ1KOAcyb6bKYFs12XtGbuGl3gvdTBpyc5hShqqLnA16EaogcIbX8D X-Received: by 10.66.186.39 with SMTP id fh7mr2686652pac.48.1443133952253; Thu, 24 Sep 2015 15:32:32 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:31 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, marc.zyngier@arm.com, christoffer.dall@linaro.org, will.deacon@arm.com, wei@redhat.com, alex.bennee@linaro.org, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Date: Thu, 24 Sep 2015 15:31:14 -0700 Message-Id: <1443133885-3366-10-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 605972e..e7f6058 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -488,6 +488,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case PMXEVCNTR_EL0: { + val = PMEVCNTR0_EL0 + vcpu_sys_reg(vcpu, PMSELR_EL0); + vcpu_sys_reg(vcpu, val) = + *vcpu_reg(vcpu, p->Rt) & 0xffffffffUL; + break; + } case PMXEVTYPER_EL0: { val = vcpu_sys_reg(vcpu, PMSELR_EL0); kvm_pmu_set_counter_event_type(vcpu, @@ -511,7 +517,17 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, break; } } else { - *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); + switch (r->reg) { + case PMXEVCNTR_EL0: { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_sys_reg(vcpu, PMSELR_EL0)); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } + default: + *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); + break; + } } return true; @@ -738,7 +754,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), trap_raz_wi }, @@ -951,6 +967,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case c9_PMXEVCNTR: { + val = c14_PMEVCNTR0 + vcpu_cp15(vcpu, c9_PMSELR); + vcpu_cp15(vcpu, val) = + *vcpu_reg(vcpu, p->Rt) & 0xffffffffUL; + break; + } case c9_PMXEVTYPER: { val = vcpu_cp15(vcpu, c9_PMSELR); kvm_pmu_set_counter_event_type(vcpu, @@ -974,7 +996,17 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, break; } } else { - *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); + switch (r->reg) { + case c9_PMXEVCNTR: { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_cp15(vcpu, c9_PMSELR)); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } + default: + *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); + break; + } } return true; @@ -1022,7 +1054,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVTYPER }, - { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMXEVCNTR }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },