From patchwork Thu Sep 24 22:31:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 7261261 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EA4CCBEEC1 for ; Thu, 24 Sep 2015 22:32:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 098D220B29 for ; Thu, 24 Sep 2015 22:32:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0EC3720B27 for ; Thu, 24 Sep 2015 22:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932152AbbIXWci (ORCPT ); Thu, 24 Sep 2015 18:32:38 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:35380 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754037AbbIXWch (ORCPT ); Thu, 24 Sep 2015 18:32:37 -0400 Received: by pacfv12 with SMTP id fv12so86496975pac.2 for ; Thu, 24 Sep 2015 15:32:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ao74XgMp/qOPXmv3G5sNpMDrJPq0pccxWAaRH+ZMMbo=; b=T5dvfCTNlh7RZ1RMvFkKUCG2ALSB8joiblEi3YsuWhsdVxpwn2HHxCugYUZGQljaXm SSgk7aZ8cS75r/Xym3J9Mwc389GtyPw6g509WXtzU2j8Br+QhlVEHPE9v/QOyN7oject eKEWW5PWfcLE/1GESFPtPFwi+98pGBUSLElIhQn1gk7vxQBoJg9DM/CXk7DrLNxNrjaZ S+b8swsJ876mOF3hHVpDe4YE2v2170A8cZ/UCLECgtzf3xztHOK+/jV80ElraJaNpgBI sS+E7s2Q4azfrehEQfd56dC9JaXomBIwpBayAQ4fhjs6pTA6/pytr18mHu+YkPODGqVu CBYQ== X-Gm-Message-State: ALoCoQnWXWMYq+VuzVzuGPfHbADbWxftZYGCVAuCF5T2Nj25PnNXABF+Fv7QlZfRZsmu0V10ajY4 X-Received: by 10.69.2.69 with SMTP id bm5mr2576769pbd.41.1443133956950; Thu, 24 Sep 2015 15:32:36 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:36 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, marc.zyngier@arm.com, christoffer.dall@linaro.org, will.deacon@arm.com, wei@redhat.com, alex.bennee@linaro.org, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Date: Thu, 24 Sep 2015 15:31:15 -0700 Message-Id: <1443133885-3366-11-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e7f6058..c38c2de 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -518,6 +518,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, } } else { switch (r->reg) { + case PMCCNTR_EL0: { + val = kvm_pmu_get_counter_value(vcpu, + ARMV8_MAX_COUNTERS - 1); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } case PMXEVCNTR_EL0: { val = kvm_pmu_get_counter_value(vcpu, vcpu_sys_reg(vcpu, PMSELR_EL0)); @@ -748,7 +754,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_pmceid, PMCEID1_EL0 }, /* PMCCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCCNTR_EL0 }, /* PMXEVTYPER_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, @@ -997,6 +1003,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, } } else { switch (r->reg) { + case c9_PMCCNTR: { + val = kvm_pmu_get_counter_value(vcpu, + ARMV8_MAX_COUNTERS - 1); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } case c9_PMXEVCNTR: { val = kvm_pmu_get_counter_value(vcpu, vcpu_cp15(vcpu, c9_PMSELR)); @@ -1051,7 +1063,8 @@ static const struct sys_reg_desc cp15_regs[] = { reset_pmceid, c9_PMCEID0 }, { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs, reset_pmceid, c9_PMCEID1 }, - { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMCCNTR }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVTYPER }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,