From patchwork Fri Oct 23 09:15:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhoujian (jay)" X-Patchwork-Id: 7471121 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E58F5BEEA4 for ; Fri, 23 Oct 2015 09:20:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2451B20445 for ; Fri, 23 Oct 2015 09:20:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 08B622041A for ; Fri, 23 Oct 2015 09:20:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752605AbbJWJRH (ORCPT ); Fri, 23 Oct 2015 05:17:07 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:5314 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751636AbbJWJRC (ORCPT ); Fri, 23 Oct 2015 05:17:02 -0400 Received: from 172.24.1.51 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.51]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BPN83463; Fri, 23 Oct 2015 17:15:44 +0800 (CST) Received: from localhost (10.177.19.14) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Fri, 23 Oct 2015 17:15:34 +0800 From: Jian Zhou To: , , , , , , , CC: , , , , Jian Zhou Subject: [PATCH v2 2/4] KVM: X86: LBR MSRs of supported CPU types Date: Fri, 23 Oct 2015 17:15:16 +0800 Message-ID: <1445591718-5720-3-git-send-email-jianjay.zhou@huawei.com> X-Mailer: git-send-email 2.6.1.windows.1 In-Reply-To: <1445591718-5720-1-git-send-email-jianjay.zhou@huawei.com> References: <1445591718-5720-1-git-send-email-jianjay.zhou@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.14] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.5629FAC1.01A8, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b9603c2889ba57f7ce45573887acedd5 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Macros about LBR MSRs. Signed-off-by: Jian Zhou Signed-off-by: Stephen He --- arch/x86/include/asm/msr-index.h | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) -- 1.7.12.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b98b471..2afcacd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -68,10 +68,32 @@ #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 +#define MSR_LBR_CORE_FROM 0x00000040 +#define MSR_LBR_CORE_TO 0x00000060 +#define MAX_NUM_LBR_MSRS 128 +/* Pentium4/Xeon(based on NetBurst) LBR */ +#define MSR_PENTIUM4_LER_FROM_LIP 0x000001d7 +#define MSR_PENTIUM4_LER_TO_LIP 0x000001d8 +#define MSR_PENTIUM4_LBR_TOS 0x000001da +#define MSR_LBR_PENTIUM4_FROM 0x00000680 +#define MSR_LBR_PENTIUM4_TO 0x000006c0 +#define SIZE_PENTIUM4_LBR_STACK 16 +/* Core2 LBR */ +#define MSR_LBR_CORE2_FROM MSR_LBR_CORE_FROM +#define MSR_LBR_CORE2_TO MSR_LBR_CORE_TO +#define SIZE_CORE2_LBR_STACK 4 +/* Atom LBR */ +#define MSR_LBR_ATOM_FROM MSR_LBR_CORE_FROM +#define MSR_LBR_ATOM_TO MSR_LBR_CORE_TO +#define SIZE_ATOM_LBR_STACK 8 +/* Nehalem LBR */ #define MSR_LBR_NHM_FROM 0x00000680 #define MSR_LBR_NHM_TO 0x000006c0 -#define MSR_LBR_CORE_FROM 0x00000040 -#define MSR_LBR_CORE_TO 0x00000060 +#define SIZE_NHM_LBR_STACK 16 +/* Skylake LBR */ +#define MSR_LBR_SKYLAKE_FROM MSR_LBR_NHM_FROM +#define MSR_LBR_SKYLAKE_TO MSR_LBR_NHM_TO +#define SIZE_SKYLAKE_LBR_STACK 32 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ #define LBR_INFO_MISPRED BIT_ULL(63)