From patchwork Wed Nov 4 14:49:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 7550741 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 83A0CBEEA4 for ; Wed, 4 Nov 2015 14:54:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 73DA2206D5 for ; Wed, 4 Nov 2015 14:54:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49F77206E8 for ; Wed, 4 Nov 2015 14:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932793AbbKDOx6 (ORCPT ); Wed, 4 Nov 2015 09:53:58 -0500 Received: from mail-wm0-f54.google.com ([74.125.82.54]:37296 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965601AbbKDOxD (ORCPT ); Wed, 4 Nov 2015 09:53:03 -0500 Received: by wmff134 with SMTP id f134so43607546wmf.0 for ; Wed, 04 Nov 2015 06:53:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34R9BmvlnW+4SuQX0UKjCIBQ7Gk1G2rh4mMlsxuu1gE=; b=qC2M0W79DiyUZzg+6sv3Uh+1eKWaBVPBrRHpwvoZA19n+BLoU1QjSSlHKVNYAGkj7H M3QHYT+KU8WcXgo+y55YSKB16rC1LCa+phclnLq7g+c2U9nP1Jy99Jd34yyMCBCoFtH6 w0mQ+ai+Kp0Jf6StqqbX22AM90NTNnOBH+rUTZw550NVG5+SqQcnaTbgiNVw8ieVmP/J n1XbPrrUh6GtbORudAKpsGUlwmmc2ZZKQ/2RZiEsXFCVtsxODaOdl8f8UKmgzhW6VMtF qKmAPH+RF2B5UniBlf/QGPwbTXRtiI8vRqhwpAyiC5CFvnr9gpWUi/Bi363Cez5wUdOn csHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34R9BmvlnW+4SuQX0UKjCIBQ7Gk1G2rh4mMlsxuu1gE=; b=mKbg8Y1lGcCxxqe8zu5+cZVhJaWxsjD16mbdLSjpK5k9B5Bzq8d+DRL4xQ8WDuuq1c rbLJa8Ez2N6DtLhnBn2sXG0E5fK+EF4RsLTSEyo0SIdgFEd5kUjDgAcqQVw8/C+h0D/N PT2FsJdvH/oPxdNL2dOAZuwR+xDNryV0wU4buEatsULLHMFtqDPM28ot9chDnpo4+DR1 UPl5VNHVRZzbGXjPGZZ23nEkb+Ebvdt10CPrN7leS5lGVVnQo1ztJa3zQahOevu4/9+e /IqbR2XBHNc9KC3l0gw92+XZWs7O/F1QPij5VxMLatoSMrQjv0geK8X53uWbrIFlZ8pd n4Rg== X-Gm-Message-State: ALoCoQkG+1n46ZkXtKuZE0QEuj/Le3sJZ7eIeck7nm0E0gOawK5EcVsDXcUk1iW/n1LZbIBkfx31 X-Received: by 10.28.141.204 with SMTP id p195mr25609048wmd.40.1446648782495; Wed, 04 Nov 2015 06:53:02 -0800 (PST) Received: from localhost.localdomain ([94.18.191.146]) by smtp.gmail.com with ESMTPSA id e9sm1985081wjw.8.2015.11.04.06.53.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Nov 2015 06:53:01 -0800 (PST) From: Christoffer Dall To: Paolo Bonzini , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Christoffer Dall Subject: [PULL 04/21] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs Date: Wed, 4 Nov 2015 15:49:43 +0100 Message-Id: <1446648600-27297-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.1.2.330.g565301e.dirty In-Reply-To: <1446648600-27297-1-git-send-email-christoffer.dall@linaro.org> References: <1446648600-27297-1-git-send-email-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Reviewed-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 367a180..f8ca2e9 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -690,10 +690,9 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, vgic_reg_access(mmio, &val, offset, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { - if (offset < 8) { - *reg = ~0U; /* Force PPIs/SGIs to 1 */ + /* Ignore writes to read-only SGI and PPI bits */ + if (offset < 8) return false; - } val = vgic_cfg_compress(val); if (offset & 4) {