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[80.11.198.90]) by smtp.gmail.com with ESMTPSA id h67sm34493865wmf.17.2015.11.19.06.54.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Nov 2015 06:54:28 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, alex.williamson@redhat.com, b.reynal@virtualopensystems.com, christoffer.dall@linaro.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: andre.przywara@arm.com, linux-kernel@vger.kernel.org, patches@linaro.org Subject: [PATCH v4 11/13] KVM: arm/arm64: vgic: implement clear active for non shared mapped IRQ Date: Thu, 19 Nov 2015 14:54:01 +0000 Message-Id: <1447944843-17731-12-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447944843-17731-1-git-send-email-eric.auger@linaro.org> References: <1447944843-17731-1-git-send-email-eric.auger@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When disabling a non shared mapped IRQs, we must manually deactivate the corresponding physical IRQ on top of removing the active state from the distributor. Signed-off-by: Eric Auger --- virt/kvm/arm/vgic.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index bd500b4..98ae15f 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -604,14 +604,34 @@ bool vgic_handle_clear_active_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, phys_addr_t offset, int vcpu_id) { - u32 *reg; + u32 *reg, orig, cleared; struct vgic_dist *dist = &kvm->arch.vgic; + struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, vcpu_id); + unsigned int i; reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); + orig = *reg; vgic_reg_access(mmio, reg, offset, ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); if (mmio->is_write) { + cleared = orig ^ *reg; + + for (i = 0; i < 32; i++) { + struct irq_phys_map *map; + unsigned int irq_num; + + if (!(cleared && (1 << i))) + continue; + irq_num = (offset * 8) + i; + map = vgic_irq_map_search(vcpu, irq_num); + if (!map || (map && map->shared)) + continue; + irq_set_irqchip_state(map->irq, + IRQCHIP_STATE_ACTIVE, + false); + } + vgic_update_state(kvm); return true; }