From patchwork Thu Jun 2 10:20:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 9149743 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D921F6074E for ; Thu, 2 Jun 2016 10:21:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC4412665D for ; Thu, 2 Jun 2016 10:21:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C13E2271FD; Thu, 2 Jun 2016 10:21:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE00D2679B for ; Thu, 2 Jun 2016 10:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932697AbcFBKV3 (ORCPT ); Thu, 2 Jun 2016 06:21:29 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33149 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932078AbcFBKV1 (ORCPT ); Thu, 2 Jun 2016 06:21:27 -0400 Received: by mail-wm0-f48.google.com with SMTP id s131so3078098wme.0 for ; Thu, 02 Jun 2016 03:21:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D9O0snTCorJoXDNQr975BSMDo09WA9f06/9NmS4eUZQ=; b=RfX+I9AaPc+8Xi3dOTmujSy+VvffKtbd536AxGaQ7bQho9fCBoNIG0JhGHFe4RJHHC TnVXIMH0C0KTqBvcRIDjUqQLKWxFY3so4OOVGuzzatcfNoAyT0YCbFf21yxFj81iXqfY rMvYjmAqHJZE9JAgMOGwuhHYwIZxjvxlxkbzY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D9O0snTCorJoXDNQr975BSMDo09WA9f06/9NmS4eUZQ=; b=N2RWM7mLHhhYDxfOoVawfumb1AfJW4JHxD/RUrLxyfBh41j7WG0qX2W2YxoIaYq0HY Tw1149/E0jmU4viIiCBem7303qqVjMRZitRTN+gHCapAP9pYs9E/lxekqQtwzttwgcGa fXqCD3uNxF+9pr0YAbdVWKMQjWe5BuJ1T7GbYP1DGg+Z5joA2/gnHL3OrxVbHqGk4lLp tGGPkbd5tXNtbmhdPNBG4DCzERdPsfeNJ9CxCouusiyDh00w3BNldpFDwHkc9/nouBzQ g/4hVZPGoOuwd0alrD9Mo2Xj8LUUOkjSCa6RHGXRQZKRJUexamVNmBdaba1JaFjHM2nI RKdw== X-Gm-Message-State: ALyK8tIs27B9rOt0V2tgn37yhBjfmE7H9a1DHJr3vO9HtIyGJ+ZdAOkrmcS7r1m4YLPdjkej X-Received: by 10.28.21.202 with SMTP id 193mr7688037wmv.92.1464862880560; Thu, 02 Jun 2016 03:21:20 -0700 (PDT) Received: from localhost.localdomain ([94.18.191.146]) by smtp.gmail.com with ESMTPSA id o129sm39552254wmb.17.2016.06.02.03.21.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Jun 2016 03:21:19 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall Subject: [PULL 7/8] arm64: KVM: vgic-v3: Relax synchronization when SRE==1 Date: Thu, 2 Jun 2016 12:20:59 +0200 Message-Id: <1464862860-1183-8-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.1.2.330.g565301e.dirty In-Reply-To: <1464862860-1183-1-git-send-email-christoffer.dall@linaro.org> References: <1464862860-1183-1-git-send-email-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marc Zyngier The GICv3 backend of the vgic is quite barrier heavy, in order to ensure synchronization of the system registers and the memory mapped view for a potential GICv2 guest. But when the guest is using a GICv3 model, there is absolutely no need to execute all these heavy barriers, and it is actually beneficial to avoid them altogether. This patch makes the synchonization conditional, and ensures that we do not change the EL1 SRE settings if we do not need to. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp/vgic-v3-sr.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c index 40c3b4c..5f8f80b 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -169,7 +169,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) * Make sure stores to the GIC via the memory mapped interface * are now visible to the system register interface. */ - dsb(st); + if (!cpu_if->vgic_sre) + dsb(st); cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); @@ -235,8 +236,12 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) val = read_gicreg(ICC_SRE_EL2); write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); - isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ - write_gicreg(1, ICC_SRE_EL1); + + if (!cpu_if->vgic_sre) { + /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ + isb(); + write_gicreg(1, ICC_SRE_EL1); + } } void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) @@ -255,8 +260,10 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) * been actually programmed with the value we want before * starting to mess with the rest of the GIC. */ - write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1); - isb(); + if (!cpu_if->vgic_sre) { + write_gicreg(0, ICC_SRE_EL1); + isb(); + } val = read_gicreg(ICH_VTR_EL2); max_lr_idx = vtr_to_max_lr_idx(val); @@ -305,8 +312,10 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) * (re)distributors. This ensure the guest will read the * correct values from the memory-mapped interface. */ - isb(); - dsb(sy); + if (!cpu_if->vgic_sre) { + isb(); + dsb(sy); + } vcpu->arch.vgic_cpu.live_lrs = live_lrs; /*