From patchwork Mon Jul 11 10:11:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Suthikulpanit, Suravee" X-Patchwork-Id: 9223229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 57EB960760 for ; Mon, 11 Jul 2016 10:45:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46C6027AC2 for ; Mon, 11 Jul 2016 10:45:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AFB927C14; Mon, 11 Jul 2016 10:45:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9696127AC2 for ; Mon, 11 Jul 2016 10:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752511AbcGKKos (ORCPT ); Mon, 11 Jul 2016 06:44:48 -0400 Received: from mail-by2nam01on0087.outbound.protection.outlook.com ([104.47.34.87]:3081 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751847AbcGKKop (ORCPT ); Mon, 11 Jul 2016 06:44:45 -0400 X-Greylist: delayed 1947 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Jul 2016 06:44:45 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=/Wi1V53zmSSD3wkk9NhFeC+3DvxpBkM7lbFfaDgBnNM=; b=T2ggy9QNdL3H120uCRofokFBBw1BWjH2YMM/vWd/6agKfBL2sH02X/pLhrAMHLtuGLVTR1dK3IK7xjbpe/7t4XAx4zyVQn3qenlcanzYbiaeDFBmwbSH62pMSGEMWX73ydlOG0oVp1e9a8IJp/CIOUgA1i8ZqZnggnq1NPmEGlw= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (124.121.8.20) by CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) with Microsoft SMTP Server (TLS) id 15.1.534.14; Mon, 11 Jul 2016 10:12:13 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit Subject: [PART2 PATCH v3 01/11] iommu/amd: Detect and enable guest vAPIC support Date: Mon, 11 Jul 2016 05:11:29 -0500 Message-ID: <1468231899-6987-2-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: SG2PR03CA0026.apcprd03.prod.outlook.com (10.160.233.36) To CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) X-MS-Office365-Filtering-Correlation-Id: 73fe1838-57fa-4212-1da2-08d3a973d5ce X-Microsoft-Exchange-Diagnostics: 1; CY1PR12MB0444; 2:kyWfN9qR20Mp5aJ67xRKTPj1jY82zmNNFlbRMNDgHRA9HbggabmKR3TPX02SqCorciKYqVllbYt03uT7pIt9c4p1i4iwr3xXH6f9ChtEd8S3xSORRVoVWIzMw4KmzjGU6TtPs3OxYyYPFrQkJE8H/iMNDD5Jj3fn9sJa7VrN7EJCfxrWiEhHjZN3eKsXNyR5; 3:TQuQsx4ifBdhrIiwqWNovjO3pOIs3CYmH/hHNGOBeWhPhafKMC0oR72a9/sACSPlgi96A9I4YiXfj1WdYJZBFlqvxTzTfSnzql6JeHb7XEwomqBmoie9+EVLh94xFmR5; 25:J7dIj4+K0Lofvd4kCvact/YKGCEkfzrGct25kcPwDUBEexgO6pSyvJjxxsCTpYTiSeic/90NH0I3xJ0QWpXzARTC0woTGGptiiM6muduv9tGdZ/E6xhv2eXVXlBK0j31iop7LzdZYgKUwV1tbUQ6uM0Qmuk2tQYD+PsGQyAHW50Y37CFU+/E7zpxO/PLlv30MO0KaXoVHDq0rSsP6iMwtfQSPc++S8rbAN7oWA5Hih9RvW4cePwKoELuvp0O8rMM/zLGKd3scb7LtA4RJIwJ4UHL+p+/zHQbenyDfaNe6unxyhp2toacNvvLSXDJaPJeoQwoXL3Zfdzr+bob3fRQvEDfQWjJc5n824tYTXrv4rJhew+eDO1Cjcr63lt94qgfewuYophGufeqGBAOlbzD/lUQTiEyzoU9u0+LbqSgFlY=; 31:O3upGwqfTNOq2mCsiMFPbvi45XhTm1AwcBcPV7G6xC9ZD97JJS/acc3Lg4SGny+yIcvCsi1g4fDJBLaH4f6LVyYleQA5bnY7SJk32yzgStvqItF6XpNHM749l1ImYq6RqCFQim6R8MEnWrW/yxVxydoOeYmF0LQPTVih67P3dfKVNq7oSWZ 4EdTzMviGtACrgaEqGcjPzo8AJ9jKRNpL4A== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR12MB0444; X-Microsoft-Exchange-Diagnostics: 1; CY1PR12MB0444; 20:a4ODTyIfS+KxiuFuYhvOQiLLmPcSOM2xh0dzhipCQlBnPL/ISYPLZNirmMcgDh1Y4zeRt82SfpIxLVZT2AUG8644zCZccqC+b5ApYbNFNHLU7Y30H1DbThEr+yo+2mTxwMVTvf6w8OyUt4LS85GkDBDj+ojcTjD3eJNTFe1rlJO9IRfx2eS9d2RlWwS332YGndEqjaprU/7YAjXrAkftaNv9sz2lLgxfVcF2cx0NfTybVhxaD1kAmKAiGagifCE+R8xJ53SjeRdcex5bJ2wO1JMD5FhwvjQmSzddUHYied5KLowUpfxLl0pdfMjMVYKvC2fLZGRwtbe2jmtfUEt4404yedZZUhthEHNP0TBpMhNPv9jIdoPXCg5ZVSiooWtcLBZgU7ji3ty5TINHe+R5FofwCHQVX2pbDXjtTXJkfVTWFvEdg/zzEzUBSTxROdEuJXwCo3O52vk6Iymdl5mFHvrDv+7nphs/T1YtAUyMBHUQy4Lwubx+m5klOoS7RZlp X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110)(211171220733660); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(8121501046)(5005006)(3002001)(10201501046)(6055026); SRVR:CY1PR12MB0444; BCL:0; PCL:0; RULEID:; SRVR:CY1PR12MB0444; X-Microsoft-Exchange-Diagnostics: 1; CY1PR12MB0444; 4:pMwortR9yXjzQ/6ruK9pOrEUgJ3VzWU+P2g6S1hVhc1Uq8iznUNLGjWEe7B9D61+UVOIwIdEAShu4NSpkG5Df36QAJ4sbKLGBznXhHPJk2sVNVIUVZiOaX6cd1uOeIXZv76XzS3sfIdWgdH/GVsnTjmuEPnXUqFovGJg0zoxO4XrRa+i58+2jTvoCFoS6RBZFTL79nFr39qIp27Vvfu9ayP1GguxX5jCEeB25D7VmtQqX7kzbKR3TyzjHFbtqlRitxTV5XHt0BIaJYCMTvD3boSNfAMAaml2zlJUg5KO1MnNye3bxEtRkLxhxdZSzmK/otTTu1Fq1vnyFi0sTFeNlydJQO03UfRgGFkUL7MFNLEY6ZoXG1wKKzunfu3JxIiHwRxkqVd/pt7Veo9RUQ21sKEDBnvbwJLaoTs+pJ1M9t05480etfdUL1eF+eDLP+syavuUK2H1KHSoc4rdxBqSQQ== X-Forefront-PRVS: 00003DBFE7 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(6069001)(7916002)(189002)(199003)(3846002)(6116002)(2201001)(101416001)(81166006)(86362001)(5003940100001)(575784001)(47776003)(586003)(189998001)(106356001)(66066001)(7736002)(77096005)(5001770100001)(36756003)(97736004)(50466002)(33646002)(50986999)(19580405001)(81156014)(305945005)(68736007)(4326007)(50226002)(19580395003)(48376002)(8676002)(105586002)(76176999)(7846002)(92566002)(42186005)(2906002)(2950100001)(229853001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR12MB0444; H:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR12MB0444; 23:gT8Jrf4xUS6wC02WFMDYVu5r9xB8v1m6+Btvm/QpA?= =?us-ascii?Q?Pa64dn+3cvN9H+IBxcLeB9oLIxOvm13CP70Yjv+XxjMFiTTnRHNc8Y87BFTs?= =?us-ascii?Q?FsEjJYisN7mMyMQ0Ehjd3HQSiRM/GifKcu8PHdavYH1D1FCJYJHmV74Nft7T?= =?us-ascii?Q?W3pkgn9C1T9P5hodzdilX9XjUwps33cDxrRfVWZ0U3cAoF8T+vsp9qo8awEa?= =?us-ascii?Q?3s+3wbQrBOCE8UUw0cANzUhjIgwcw/jWTnlpV4gTwyOaZHAuxcJS8NmsSspx?= =?us-ascii?Q?3w6QRk4xlr+NHmh9Hs6n6VXEiSzUY7ZpgwFfwgPZCWYgyHa6f57hciA+3aON?= =?us-ascii?Q?B3Y56zBJjfTd571BOgJNbqlito7I4M/+NlEoV0OWpiZH4tupifM6WKx6CUNr?= =?us-ascii?Q?sdZZvc5fvYdOQyTWmlKygJTc45qxu0MHOAyIV4bGzx6YQ0Fng86DFIB9j8Xv?= =?us-ascii?Q?Mrm2v91++hhkntVmFOUQ9NhZYpq9x8dCUsh7t689JGUKzSynp2aDOcOrNkEq?= =?us-ascii?Q?xxeO+nS5tR/11L6cXHGPNUjzfWpYwnsdBoL+N3TpbrLz1XAd3pg2cwLitEbK?= =?us-ascii?Q?BtKMAB+1kVzKVarlq3DV0i5bCD+gH4aQGxMzAi3PWI1kBnWiXiBbSIMUqIg7?= =?us-ascii?Q?v4g+K5ksyPVJemM+myUoWjCHsQOLvym9wIq8EBGngkmcy25OKl/SXJ9bvXY/?= =?us-ascii?Q?KtVivxeaYwRmK5pmbeWm+I0J24192jMkIIt0CwHXvdDAVCpGIkPT7wVgY6qM?= =?us-ascii?Q?gF2M/jfXicF/qLTb1LZfxsd0ux/5sKJRnC7qN2gsIAYIUcmfji47889D9HWT?= =?us-ascii?Q?0DgL2+t9LmQCLA8RmO5FoXOxGCgpi3dc6QY/0puf/FOGZS+HIDq7Qcp8ixVe?= =?us-ascii?Q?QlSGlc8Yrp7mQ7R/3x1jmgiAe/4rdY2+wKr9X4IeTgiJVrL18nCNOnoFAUGi?= =?us-ascii?Q?+sA3JCVXMUYK00wE/SKVBIRDB//YcqwZD1/wH4W6eryNSoXTl20sLyEboukB?= =?us-ascii?Q?k84TKK6W2ScLt9cwDMylnY2kmkDa343RyCCJWa240+2udrmjC70bximsRoiY?= =?us-ascii?Q?sh8R27jTtzHkgICFYKqiJ6FJtbele9vTUqCMycxvJOTPEl6xUHPShTpS/MFA?= =?us-ascii?Q?tOsZ3kkMCA=3D?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR12MB0444; 6:A9MjswGeU2WmsG4HCmqPJLpgtH1xG4V9lFUDVnLOD2i15V3K5yH51PicPQb+sJNljnStY0fcR40uEIX/ZDCaAuh4cLA9nuVuiHoSEsAkxA/LgMT3Dcqi64V1D11C246vk+QZkUeBhkMV4RbYLtJrPEMv9hdt2FoIp7CcxAvN8nYZtRYBLnmXKeWTHBus6wyidifh1TekMouXu5a3VoZZZI3tSdX5zO16bXYawA3Bi52J8W8HkRDkRe2tFrN5Dam1GQ7cqdcbtXatFpDI4vbEGWuNABH+UeUXaf9t1HMwzRggH6Ofvo3+psmtsXJ4B4vx50yR5AOLZIroZe2okPm6Cw==; 5:K8Bp5eZnd/rcx3t5DkotLP35WsxUs1CUL7O3oQNX0ooHydoxiWt4Dwbygquciov2+tD8VMLJUyOjB0lPAmjRd0VjrDniWgUQd+03bx6QDWL6txNTnuGyDCIdrElk0s4948PbY5Fjugm0xpCAvpxacA==; 24:a3VnGmodyazs6Fyyql+rttEw6Feg/0sAC69S/7l3ngLxjouGVFTEwIIex89Rvlf63ECNDfvglMltQXvCx+Vh7nbpcCyoH91Tq03uEMkOeSc=; 7:rCFuG+3xOIHHey3ovUNDl6AAelbKPk00UDWCM2EKXLcfDUITBGzBS9tfE+ezG2O0VlJfzHqkgbEVzWlcq4WJGyHM3YfANwnA1SGNvcvBp0AsZb3Xup4CerRJhxyN80moGZezM+4iFvt/OZAOy1XPH3CImSkd89gh9nfbwYCBmGYFkAKZUPBsqB/+mRwEqeqKRk/UfCPtoii5exvZ3bLipOWphPF9UIbcttuq/FiRQeniEFYrK6HOvrp9+5bscDCt SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY1PR12MB0444; 20:v+wq/qnYAo0koxFwlzVvs3Tu3nsHP4L44vpC5Z5Ed0zTiYVaUrOkTNMpOwtcTkbtx7U5Fo9Np03kPejYrrMPGZmTPHHoneWvOdIlhKbj9efCQPsCq2yDHaYubqano5UYQWAhhTeuGS1zZHdZLhkJ5h85R5T/mwk97ef8HSM+z0gWLf2m3xax7Zeg6sU/tXiLPtVacLV4Sah+mfhcoOxeWIMiDe5bHWurgx0zS1iMrM8B0X32Q4M6D3tG/VwSFGlW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2016 10:12:13.6756 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB0444 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Suravee Suthikulpanit This patch introduces a new IOMMU driver parameter, amd_iommu_guest_ir, which can be used to specify different interrupt remapping mode for passthrough devices to VM guest: * legacy: Legacy interrupt remapping (w/ 32-bit IRTE) * vapic : Guest vAPIC interrupt remapping (w/ GA mode 128-bit IRTE) Note that in vapic mode, it can also supports legacy interrupt remapping for non-passthrough devices with the 128-bit IRTE. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu_init.c | 73 +++++++++++++++++++++++++++++++++++++---- drivers/iommu/amd_iommu_proto.h | 1 + drivers/iommu/amd_iommu_types.h | 24 ++++++++++++++ 3 files changed, 92 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index d091def..d0930b1 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -145,6 +145,8 @@ struct ivmd_header { bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; +int amd_iommu_guest_ir; + static bool amd_iommu_detected; static bool __initdata amd_iommu_disabled; static int amd_iommu_target_ivhd_type; @@ -1258,6 +1260,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) iommu->mmio_phys_end = MMIO_REG_END_OFFSET; else iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; + if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) + amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; break; case 0x11: case 0x40: @@ -1265,6 +1269,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) iommu->mmio_phys_end = MMIO_REG_END_OFFSET; else iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; + if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) + amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; break; default: return -EINVAL; @@ -1488,6 +1494,14 @@ static int iommu_init_pci(struct amd_iommu *iommu) if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) return -ENOMEM; + /* Note: We have already checked GASup from IVRS table. + * Now, we need to make sure that GAMSup is set. + */ + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + !iommu_feature(iommu, FEATURE_GAM_VAPIC)) + amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; + + if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) amd_iommu_np_cache = true; @@ -1545,16 +1559,24 @@ static void print_iommu_info(void) dev_name(&iommu->dev->dev), iommu->cap_ptr); if (iommu->cap & (1 << IOMMU_CAP_EFR)) { - pr_info("AMD-Vi: Extended features: "); + pr_info("AMD-Vi: Extended features (%#llx):\n", + iommu->features); for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { if (iommu_feature(iommu, (1ULL << i))) pr_cont(" %s", feat_str[i]); } + + if (iommu->features & FEATURE_GAM_VAPIC) + pr_cont(" GA_vAPIC"); + pr_cont("\n"); } } - if (irq_remapping_enabled) + if (irq_remapping_enabled) { pr_info("AMD-Vi: Interrupt remapping enabled\n"); + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + pr_info("AMD-Vi: virtual APIC enabled\n"); + } } static int __init amd_iommu_init_pci(void) @@ -1852,6 +1874,22 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu) iommu->stored_addr_lo | 1); } +static void iommu_enable_ga(struct amd_iommu *iommu) +{ +#ifdef CONFIG_IRQ_REMAP + switch (amd_iommu_guest_ir) { + case AMD_IOMMU_GUEST_IR_VAPIC: + iommu_feature_enable(iommu, CONTROL_GAM_EN); + /* Fall through */ + case AMD_IOMMU_GUEST_IR_LEGACY_GA: + iommu_feature_enable(iommu, CONTROL_GA_EN); + break; + default: + break; + } +#endif +} + /* * This function finally enables all IOMMUs found in the system after * they have been initialized @@ -1867,6 +1905,7 @@ static void early_enable_iommus(void) iommu_enable_command_buffer(iommu); iommu_enable_event_buffer(iommu); iommu_set_exclusion_range(iommu); + iommu_enable_ga(iommu); iommu_enable(iommu); iommu_flush_all_caches(iommu); } @@ -2147,10 +2186,16 @@ static int __init early_amd_iommu_init(void) * remapping tables. */ ret = -ENOMEM; - amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", - MAX_IRQS_PER_TABLE * sizeof(u32), - IRQ_TABLE_ALIGNMENT, - 0, NULL); + if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) + amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", + MAX_IRQS_PER_TABLE * sizeof(u32), + IRQ_TABLE_ALIGNMENT, + 0, NULL); + else + amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", + MAX_IRQS_PER_TABLE * (sizeof(u64) * 2), + IRQ_TABLE_ALIGNMENT, + 0, NULL); if (!amd_iommu_irq_cache) goto out; @@ -2403,6 +2448,21 @@ static int __init parse_amd_iommu_dump(char *str) return 1; } +static int __init parse_amd_iommu_intr(char *str) +{ + for (; *str; ++str) { + if (strncmp(str, "legacy", 6) == 0) { + amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; + break; + } + if (strncmp(str, "vapic", 5) == 0) { + amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; + break; + } + } + return 1; +} + static int __init parse_amd_iommu_options(char *str) { for (; *str; ++str) { @@ -2511,6 +2571,7 @@ static int __init parse_ivrs_acpihid(char *str) __setup("amd_iommu_dump", parse_amd_iommu_dump); __setup("amd_iommu=", parse_amd_iommu_options); +__setup("amd_iommu_intr=", parse_amd_iommu_intr); __setup("ivrs_ioapic", parse_ivrs_ioapic); __setup("ivrs_hpet", parse_ivrs_hpet); __setup("ivrs_acpihid", parse_ivrs_acpihid); diff --git a/drivers/iommu/amd_iommu_proto.h b/drivers/iommu/amd_iommu_proto.h index 0bd9eb3..faa3b48 100644 --- a/drivers/iommu/amd_iommu_proto.h +++ b/drivers/iommu/amd_iommu_proto.h @@ -38,6 +38,7 @@ extern int amd_iommu_enable(void); extern void amd_iommu_disable(void); extern int amd_iommu_reenable(int); extern int amd_iommu_enable_faulting(void); +extern int amd_iommu_guest_ir; /* IOMMUv2 specific functions */ struct iommu_domain; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 590956a..25f939b 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -92,6 +92,7 @@ #define FEATURE_GA (1ULL<<7) #define FEATURE_HE (1ULL<<8) #define FEATURE_PC (1ULL<<9) +#define FEATURE_GAM_VAPIC (1ULL<<21) #define FEATURE_PASID_SHIFT 32 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) @@ -146,6 +147,8 @@ #define CONTROL_PPFINT_EN 0x0eULL #define CONTROL_PPR_EN 0x0fULL #define CONTROL_GT_EN 0x10ULL +#define CONTROL_GA_EN 0x11ULL +#define CONTROL_GAM_EN 0x19ULL #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) #define CTRL_INV_TO_NONE 0 @@ -329,6 +332,12 @@ #define IOMMU_CAP_NPCACHE 26 #define IOMMU_CAP_EFR 27 +/* IOMMU Feature Reporting Field (for IVHD type 10h */ +#define IOMMU_FEAT_GASUP_SHIFT 6 + +/* IOMMU Extended Feature Register (EFR) */ +#define IOMMU_EFR_GASUP_SHIFT 7 + #define MAX_DOMAIN_ID 65536 /* Protection domain flags */ @@ -682,4 +691,19 @@ static inline int get_hpet_devid(int id) return -EINVAL; } +enum amd_iommu_intr_mode_type { + AMD_IOMMU_GUEST_IR_LEGACY, + + /* This mode is not visible to users. It is used when + * we cannot fully enable vAPIC and fallback to only support + * legacy interrupt remapping via 128-bit IRTE. + */ + AMD_IOMMU_GUEST_IR_LEGACY_GA, + AMD_IOMMU_GUEST_IR_VAPIC, +}; + +#define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ + x == AMD_IOMMU_GUEST_IR_LEGACY_GA) + +#define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */