From patchwork Wed Sep 14 07:58:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wanpeng Li X-Patchwork-Id: 9330775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B151E6077F for ; Wed, 14 Sep 2016 07:59:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A326329A92 for ; Wed, 14 Sep 2016 07:59:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 97E1E29A96; Wed, 14 Sep 2016 07:59:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3841229A92 for ; Wed, 14 Sep 2016 07:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758789AbcINH7N (ORCPT ); Wed, 14 Sep 2016 03:59:13 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35501 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751790AbcINH7L (ORCPT ); Wed, 14 Sep 2016 03:59:11 -0400 Received: by mail-pf0-f194.google.com with SMTP id z84so411254pfi.2; Wed, 14 Sep 2016 00:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eagRRvbXuUi1MiVNtLsVPoFsAjBPb6tPAW3qavEimjA=; b=OHYHgWxnnC4TDaBInfv1w9O9ocfT/pMNS5sXU/lZ5fGgjVS7XzU45f07ojWlQTMiwA rdhVjGXBP5+4yTlp++HlSHLF5so5f/H97o4zQT++Qa1WHzSipToGHyIwqzhnkw5S2Imt VCqAlB5leckCFXlCJEciOcQ1gEqUtP55yjBQl9MnvvVqhc8b7NxQ6KKIrV9pN3b4w25C XJrQdqto1Wyfq5Fm5yEPHkDHlH+Ruf/VWIZDlYG4izIbRyoeRYJXCK0Y0uYM7z2HsJ0d mtQUW84v0ofzP8KSjo+8l7lE7zSx7eyk/Sxdg2lYZ49rjNngU2LkQjtGMxTwcfB5QyUC cOmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eagRRvbXuUi1MiVNtLsVPoFsAjBPb6tPAW3qavEimjA=; b=NuMFBpDYb4juBDb96Ag8beHb/M3Cnei1rPaj/IaV4PUpj3ala50zdjXRbzLL5KLUIV AFj22+ayEUDJfNzj3VAdyoVplcnZhgL+va3A51dncHDyVpo2xVtWlNPiRK5uqQccYA8+ 23bDgTO8yPgQHbObTahY90jVls18n9vgOyK0zqdEHzJ6MDGGKhn1m/QwhUWC+/pa/l3j d8oNLPn0H7s++bkJVjVPHR5hMdS6A2nLCGh0Dc8npiP2CVZXMOaR4t1ydagNqA9no5/6 e8JZW3LHlmxhJ88Q3V5oweM7LJO5/9CSuWAmxgmlfQV6nRKJ28lzqjmm8+mhWePi9LVe Lddg== X-Gm-Message-State: AE9vXwPxj162lPhCLIiu9TAQ9sRXs04bzmCZy9KKeHFhy8nXwZVOavf2DRN/JK1IfCR4FQ== X-Received: by 10.98.18.8 with SMTP id a8mr2131070pfj.57.1473839950724; Wed, 14 Sep 2016 00:59:10 -0700 (PDT) Received: from kernel.kingsoft.cn ([114.255.44.132]) by smtp.gmail.com with ESMTPSA id v29sm35900197pfd.65.2016.09.14.00.59.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Sep 2016 00:59:09 -0700 (PDT) From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Wanpeng Li , Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wincy Van , Yang Zhang Subject: [PATCH] KVM: VMX: Enable MSR-BASED TPR shadow even if w/o APICv Date: Wed, 14 Sep 2016 15:58:56 +0800 Message-Id: <1473839936-3393-1-git-send-email-wanpeng.li@hotmail.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wanpeng Li I observed that kvmvapic(to optimize flexpriority=N or AMD) is used to boost TPR access when testing kvm-unit-test/eventinj.flat tpr case on my haswell desktop (w/ flexpriority, w/o APICv). Commit (8d14695f9542 x86, apicv: add virtual x2apic support) disable virtual x2apic mode completely if w/o APICv, and the author also told me that windows guest can't enter into x2apic mode when he developed the APICv feature several years ago. However, it is not truth currently, Interrupt Remapping and vIOMMU is added to qemu and the developers from Intel test windows 8 can work in x2apic mode w/ Interrupt Remapping enabled recently. This patch enables TPR shadow for virtual x2apic mode to boost windows guest in x2apic mode even if w/o APICv. Can pass the kvm-unit-test. Suggested-by: Wincy Van Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Wincy Van Cc: Yang Zhang Signed-off-by: Wanpeng Li --- arch/x86/kvm/vmx.c | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 5cede40..e703129 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -6336,7 +6336,7 @@ static void wakeup_handler(void) static __init int hardware_setup(void) { - int r = -ENOMEM, i, msr; + int r = -ENOMEM, i; rdmsrl_safe(MSR_EFER, &host_efer); @@ -6464,18 +6464,6 @@ static __init int hardware_setup(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - for (msr = 0x800; msr <= 0x8ff; msr++) - vmx_disable_intercept_msr_read_x2apic(msr); - - /* TMCCT */ - vmx_enable_intercept_msr_read_x2apic(0x839); - /* TPR */ - vmx_disable_intercept_msr_write_x2apic(0x808); - /* EOI */ - vmx_disable_intercept_msr_write_x2apic(0x80b); - /* SELF-IPI */ - vmx_disable_intercept_msr_write_x2apic(0x83f); - if (enable_ept) { kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, @@ -8435,12 +8423,7 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) return; } - /* - * There is not point to enable virtualize x2apic without enable - * apicv - */ - if (!cpu_has_vmx_virtualize_x2apic_mode() || - !kvm_vcpu_apicv_active(vcpu)) + if (!cpu_has_vmx_virtualize_x2apic_mode()) return; if (!cpu_need_tpr_shadow(vcpu)) @@ -8449,8 +8432,28 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); if (set) { + int msr; + sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; + + if (kvm_vcpu_apicv_active(vcpu)) { + for (msr = 0x800; msr <= 0x8ff; msr++) + vmx_disable_intercept_msr_read_x2apic(msr); + + /* TMCCT */ + vmx_enable_intercept_msr_read_x2apic(0x839); + /* TPR */ + vmx_disable_intercept_msr_write_x2apic(0x808); + /* EOI */ + vmx_disable_intercept_msr_write_x2apic(0x80b); + /* SELF-IPI */ + vmx_disable_intercept_msr_write_x2apic(0x83f); + } else if (vmx_exec_control(to_vmx(vcpu)) & CPU_BASED_TPR_SHADOW) { + /* TPR */ + vmx_disable_intercept_msr_read_x2apic(0x808); + vmx_disable_intercept_msr_write_x2apic(0x808); + } } else { sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;