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Thu, 2 Mar 2017 15:14:28 +0000 Subject: [RFC PATCH v2 10/32] x86: DMA support for SEV memory encryption From: Brijesh Singh To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Thu, 2 Mar 2017 10:14:25 -0500 Message-ID: <148846766532.2349.4832844575566575886.stgit@brijesh-build-machine> In-Reply-To: <148846752022.2349.13667498174822419498.stgit@brijesh-build-machine> References: <148846752022.2349.13667498174822419498.stgit@brijesh-build-machine> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR09CA0043.namprd09.prod.outlook.com (10.172.184.157) To CY4PR12MB1605.namprd12.prod.outlook.com (10.172.72.14) X-MS-Office365-Filtering-Correlation-Id: e85901fe-fee4-49b9-ac10-08d4617ed330 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081); SRVR:CY4PR12MB1605; X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1605; 3:fX84n/Y4NzmggOCHussRUTwD+ea31TyqypqfD6j8BcRbyXUrYv7xBsF9bvzrdoguI+wRS522xT9DPPgZZYTrz1pKe8U9sTHXpcyDDJIKJcnXpwMPeVGSS/C2MNi66rbN/xOIitAZbGltwHAj2QXHArIWPP4DW5WjjKC6HRUH/sjyZkBQ7f/eOKzEa7xO3mA8mEa0lpKyhGhUK2sVUHRwTldR5VO+w93g1piIkog8xSU58M2Rrydp8Op6krYESwaMr90/Mt9QWMo7KZBcr2JsHPuaRuSxj6v2jShwCd25KzY=; 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20:4hOz1aWx9QhTvRiqvCqckD8vF4t2yLjRbWO9JNP7KZB5Lgk20FMgpyWIYOMJjkXKAnfCxgmYety0kTpZ0JxHYtvnkGDqFkzWqGl4xUNCssp0VHHej3qdmD05GwnOFQYOewEhr9ERMCx8ROTEI6SPwCqKyQAvqOmz6HqJsKOE5UGQ7GaPuKFh/s1fetzqFAMZLk1OV8tfNDahJzBVVGniGXMLGpyAMW41W9Ae4VJt5Kq6EwGt2mwNIT78b3QitfN8 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2017 15:14:28.2725 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1605 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tom Lendacky DMA access to memory mapped as encrypted while SEV is active can not be encrypted during device write or decrypted during device read. In order for DMA to properly work when SEV is active, the swiotlb bounce buffers must be used. Signed-off-by: Tom Lendacky --- arch/x86/mm/mem_encrypt.c | 77 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 090419b..7df5f4c 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -197,8 +197,81 @@ void __init sme_early_init(void) /* Update the protection map with memory encryption mask */ for (i = 0; i < ARRAY_SIZE(protection_map); i++) protection_map[i] = pgprot_encrypted(protection_map[i]); + + if (sev_active()) + swiotlb_force = SWIOTLB_FORCE; +} + +static void *sme_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t gfp, unsigned long attrs) +{ + unsigned long dma_mask; + unsigned int order; + struct page *page; + void *vaddr = NULL; + + dma_mask = dma_alloc_coherent_mask(dev, gfp); + order = get_order(size); + + gfp &= ~__GFP_ZERO; + + page = alloc_pages_node(dev_to_node(dev), gfp, order); + if (page) { + dma_addr_t addr; + + /* + * Since we will be clearing the encryption bit, check the + * mask with it already cleared. + */ + addr = phys_to_dma(dev, page_to_phys(page)) & ~sme_me_mask; + if ((addr + size) > dma_mask) { + __free_pages(page, get_order(size)); + } else { + vaddr = page_address(page); + *dma_handle = addr; + } + } + + if (!vaddr) + vaddr = swiotlb_alloc_coherent(dev, size, dma_handle, gfp); + + if (!vaddr) + return NULL; + + /* Clear the SME encryption bit for DMA use if not swiotlb area */ + if (!is_swiotlb_buffer(dma_to_phys(dev, *dma_handle))) { + set_memory_decrypted((unsigned long)vaddr, 1 << order); + *dma_handle &= ~sme_me_mask; + } + + return vaddr; } +static void sme_free(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle, unsigned long attrs) +{ + /* Set the SME encryption bit for re-use if not swiotlb area */ + if (!is_swiotlb_buffer(dma_to_phys(dev, dma_handle))) + set_memory_encrypted((unsigned long)vaddr, + 1 << get_order(size)); + + swiotlb_free_coherent(dev, size, vaddr, dma_handle); +} + +static struct dma_map_ops sme_dma_ops = { + .alloc = sme_alloc, + .free = sme_free, + .map_page = swiotlb_map_page, + .unmap_page = swiotlb_unmap_page, + .map_sg = swiotlb_map_sg_attrs, + .unmap_sg = swiotlb_unmap_sg_attrs, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = swiotlb_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = swiotlb_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, +}; + /* Architecture __weak replacement functions */ void __init mem_encrypt_init(void) { @@ -208,6 +281,10 @@ void __init mem_encrypt_init(void) /* Call into SWIOTLB to update the SWIOTLB DMA buffers */ swiotlb_update_mem_attributes(); + /* Use SEV DMA operations if SEV is active */ + if (sev_active()) + dma_ops = &sme_dma_ops; + pr_info("AMD Secure Memory Encryption (SME) active\n"); }