From patchwork Tue Sep 26 10:20:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wanpeng Li X-Patchwork-Id: 9971649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3496460365 for ; Tue, 26 Sep 2017 10:21:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E93528E66 for ; Tue, 26 Sep 2017 10:21:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2382928E7C; Tue, 26 Sep 2017 10:21:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2A6F28E66 for ; Tue, 26 Sep 2017 10:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754534AbdIZKVP (ORCPT ); Tue, 26 Sep 2017 06:21:15 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:35446 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754497AbdIZKUq (ORCPT ); Tue, 26 Sep 2017 06:20:46 -0400 Received: by mail-pf0-f196.google.com with SMTP id i23so4829493pfi.2; Tue, 26 Sep 2017 03:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=74ANCkvnpvOb1QBncL0OPvbTlPwUom32tCPwFCCviRM=; b=vIB8D/JuahNnnnD9cOI3BrVGBkuMgFdrVJQz1l10dbDAxMg+O+R3T2b8u7jWrV1DH8 wgeY+C2uyf+UhXNg9HSfH4tkZWpSljyLREDrrMjEPVyGslzRZYgOLgR+sEzvbnXkgeVV FJEzf99VEBD5LGaJDNIN/RpS9UDWiky5Y9XqsqpiDAc3siKZcIqKbHr40oxAh2X+1oYn oNbFrrZU84KHSBuXD70xCmLDHKmgITluraO4VZbvwqN5cQGsLRDCIibZ7qvbhSRoDw9D D8Q3fTXCxmCVkG8T0EKIny2ORZ3zcmeykg/DsN1NEbQyQqIqsOPuHnZ0u+bwGKbPxm9u nz6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=74ANCkvnpvOb1QBncL0OPvbTlPwUom32tCPwFCCviRM=; b=cyGTTVfkGnhUvPIhjw5q8dcPw9eQxbqM+xRJsHCn8hzojtbgOLPvH7Z2aVyJfz2Faj alkBc41XMNuQn0gXo+kF6oxIoh2f7gHx4AoH8cXhWn0roMeAjoFYQseT0j72dno0s6Vg Y0UHhj98hLIweRfKmW6VYJm6tHSosajYDEAeXkVjHji0E0gUNympbPlLZz5SM4psVVqO I3sKY56LJwZXJr3/mwbAqIxwGfO98OcRMIP/iWjUVx5RBHJdt0UbehZeMZNQDivk0vTf E2PzyZ7Pfzq3yd8VpjfvBkPBwL+9DeeYeGMQ/gNbMwfDdJ69l1Q3lnL2dHbsBrNlWRCS IvgQ== X-Gm-Message-State: AHPjjUgH9IinAIynE/hdF2qCpDG2NybXCUrsbQvqFiNy3SyYNY4rIKjQ ukPTY2bIFjOXmU3ntr6YKPPYfw== X-Google-Smtp-Source: AOwi7QDpIdNdeWPVrWUeSwmeu/7g4e1mvf07pE62E1b8Ndd3vXzjJUdha1VLQK8YdCArJ06Cs7whbQ== X-Received: by 10.84.224.75 with SMTP id a11mr10360003plt.106.1506421245839; Tue, 26 Sep 2017 03:20:45 -0700 (PDT) Received: from localhost ([203.205.141.123]) by smtp.gmail.com with ESMTPSA id l12sm15313584pgr.10.2017.09.26.03.20.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Sep 2017 03:20:45 -0700 (PDT) From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wanpeng Li Subject: [PATCH 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer Date: Tue, 26 Sep 2017 03:20:32 -0700 Message-Id: <1506421232-21246-3-git-send-email-wanpeng.li@hotmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506421232-21246-1-git-send-email-wanpeng.li@hotmail.com> References: <1506421232-21246-1-git-send-email-wanpeng.li@hotmail.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wanpeng Li The description in the Intel SDM of how the divide configuration register is used: "The APIC timer frequency will be the processor's bus clock or core crystal clock frequency divided by the value specified in the divide configuration register." Observation of baremetal shown that when the TDCR is change, the TMCCT does not change or make a big jump in value, but the rate at which it count down change. The patch update the emulation to APIC timer to so that a change to the divide configuration would be reflected in the value of the counter and when the next interrupt is triggered. Cc: Paolo Bonzini Cc: Radim Krčmář Signed-off-by: Wanpeng Li --- arch/x86/kvm/lapic.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 946c11b..6bafd06 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1432,7 +1432,7 @@ static void start_sw_period(struct kvm_lapic *apic) HRTIMER_MODE_ABS_PINNED); } -static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) +static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update, uint32_t old_divisor) { ktime_t now, remaining; u64 tscl = rdtsc(), delta; @@ -1440,7 +1440,7 @@ static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) /* Calculate the next time the timer should trigger an interrupt */ now = ktime_get(); apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) - * APIC_BUS_CYCLE_NS * apic->divide_count; + * APIC_BUS_CYCLE_NS * old_divisor; if (!apic->lapic_timer.period) return false; @@ -1485,6 +1485,12 @@ static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) if (!delta) return false; + if (apic->divide_count != old_divisor) { + apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) + * APIC_BUS_CYCLE_NS * apic->divide_count; + delta = delta * apic->divide_count / old_divisor; + } + apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + nsec_to_cycles(apic->vcpu, delta); apic->lapic_timer.target_expiration = ktime_add_ns(now, delta); @@ -1624,12 +1630,13 @@ void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) restart_apic_timer(apic); } -static void start_apic_timer(struct kvm_lapic *apic, bool timer_update) +static void start_apic_timer(struct kvm_lapic *apic, bool timer_update, + uint32_t old_divisor) { atomic_set(&apic->lapic_timer.pending, 0); if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) - && !set_target_expiration(apic, timer_update)) + && !set_target_expiration(apic, timer_update, old_divisor)) return; restart_apic_timer(apic); @@ -1745,7 +1752,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); kvm_lapic_set_reg(apic, APIC_LVTT, val); if (apic_update_lvtt(apic) && !apic_lvtt_tscdeadline(apic)) - start_apic_timer(apic, true); + start_apic_timer(apic, true, apic->divide_count); break; case APIC_TMICT: @@ -1754,16 +1761,20 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) hrtimer_cancel(&apic->lapic_timer.timer); kvm_lapic_set_reg(apic, APIC_TMICT, val); - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); break; - case APIC_TDCR: + case APIC_TDCR: { + uint32_t current_divisor = apic->divide_count; + if (val & 4) apic_debug("KVM_WRITE:TDCR %x\n", val); kvm_lapic_set_reg(apic, APIC_TDCR, val); update_divide_count(apic); + hrtimer_cancel(&apic->lapic_timer.timer); + start_apic_timer(apic, true, current_divisor); break; - + } case APIC_ESR: if (apic_x2apic_mode(apic) && val != 0) { apic_debug("KVM_WRITE:ESR not zero %x\n", val); @@ -1888,7 +1899,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) hrtimer_cancel(&apic->lapic_timer.timer); apic->lapic_timer.tscdeadline = data; - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); } void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) @@ -2254,7 +2265,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) apic_update_lvtt(apic); apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); update_divide_count(apic); - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); apic->irr_pending = true; apic->isr_count = vcpu->arch.apicv_active ? 1 : count_vectors(apic->regs + APIC_ISR);