From patchwork Tue Oct 3 03:11:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 9981489 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 61AFF60384 for ; Tue, 3 Oct 2017 03:14:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 398761FF12 for ; Tue, 3 Oct 2017 03:14:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C7B728823; Tue, 3 Oct 2017 03:14:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFBEA287BD for ; Tue, 3 Oct 2017 03:14:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752106AbdJCDNy (ORCPT ); Mon, 2 Oct 2017 23:13:54 -0400 Received: from mail-it0-f51.google.com ([209.85.214.51]:46922 "EHLO mail-it0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbdJCDMI (ORCPT ); Mon, 2 Oct 2017 23:12:08 -0400 Received: by mail-it0-f51.google.com with SMTP id d192so9964384itd.1 for ; Mon, 02 Oct 2017 20:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GwIjgmGyYytntsQMjHz3GfddpVQgMG9v/6siaXcoTCM=; b=CzoltiCdDm/aeN0Vvl9lBSUUwW9Oqtk3oEWMIbeLXEXPDchlaZ+nHJ4ao4HLaN+pJQ HmTKQZL1OX+4RMSCn8KtSk7xU+1aJTH/QjDm8TH7RCVE4DJt4Xgq9dRLWTCSQcH3SGGR IvqOf0c5SFBwiWybpJYS4YXgJrA9xwEU6sAZk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GwIjgmGyYytntsQMjHz3GfddpVQgMG9v/6siaXcoTCM=; b=UNmGZBHpgbhikp7COHIkKtFMGYdrBF0iylPf0eX9AnVE4yXxMYuNw+juSPcqah0jvV wd/D4VrTpNL2W76LrjMFI3acLKr3oW0R8ANJaC7Nek5MTZi50jGHLrdMbsqHTTqW0ojN G9ZcB0Ukm3SZkb3oZW6naSr3NjyjkfDYcwfEqNnml06Vjev4qB57x7lvHPHvJvwGYNvF JMVGr6R71lVEwnTGyVRUtK6mz/llM0R/a3C8kS5Z57p/3Rv+WjToUznp9Gi0/ovLlH+J ji4ntNv+EueWMCbPXUF1VINmIH7NSt5DBLARBFZefPV25IfDWUfAQ2wIkeZmvsjEiHN3 YOyw== X-Gm-Message-State: AHPjjUiGco/ICNFrmGJyiIX10saBa2iTE+WfSDG2/84v1CNQO7mKahNb ihkX2BqkzhRJ8zJL0ZNB0Jxnlg== X-Google-Smtp-Source: AOwi7QChTBR5scZ6ObkIGr5hmPRlHv8iySR1OZE7/9RR155JVLk2bQhY3K3S5V0DMDYejP7WNGisow== X-Received: by 10.36.83.20 with SMTP id n20mr23810404itb.120.1507000327823; Mon, 02 Oct 2017 20:12:07 -0700 (PDT) Received: from node.jintackl-qv28633.kvmarm-pg0.wisc.cloudlab.us (c220g1-031126.wisc.cloudlab.us. [128.104.222.76]) by smtp.gmail.com with ESMTPSA id h84sm5367193iod.72.2017.10.02.20.12.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Oct 2017 20:12:07 -0700 (PDT) From: Jintack Lim To: christoffer.dall@linaro.org, marc.zyngier@arm.com, kvmarm@lists.cs.columbia.edu Cc: jintack@cs.columbia.edu, pbonzini@redhat.com, rkrcmar@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jintack Lim Subject: [RFC PATCH v2 26/31] KVM: arm64: Emulate TLBI ALLE1(IS) Date: Mon, 2 Oct 2017 22:11:08 -0500 Message-Id: <1507000273-3735-24-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> References: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP TLBI ALLE1(IS) instruction invalidates all EL1&0 regime stage 1 and 2 TLB entries (on all PEs in the same Inner Shareable domain). To emulate these instructions, we first need to clear all the mappings in the shadow page tables since executing those instructions implies the change of mappings in the stage 2 page tables maintained by the guest hypervisor. We then need to invalidate all EL1&0 regime stage 1 and 2 TLB entries of all VMIDs, which are assigned by the host hypervisor, for this VM. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a1ae8fb..5a82de9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1795,6 +1795,31 @@ static bool handle_vae2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } +static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + struct kvm_s2_mmu *mmu = &vcpu->kvm->arch.mmu; + u64 vttbr = kvm_get_vttbr(&mmu->vmid, mmu); + + if (vcpu->kvm->arch.mmu.vmid.vmid_gen) { + /* + * Invalidate the stage 1 and 2 TLB entries for the host OS + * in a VM only if there is one. + */ + kvm_call_hyp(__kvm_tlb_flush_vmid, vttbr); + } + + spin_lock(&vcpu->kvm->mmu_lock); + /* + * Clear all mappings in the shadow page tables and invalidate the stage + * 1 and 2 TLB entries via kvm_tlb_flush_vmid_ipa(). + */ + kvm_nested_s2_clear(vcpu->kvm); + spin_unlock(&vcpu->kvm->mmu_lock); + + return true; +} + /* * AT instruction emulation * @@ -1880,14 +1905,14 @@ static bool handle_vae2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, SYS_INSN_TO_DESC(TLBI_IPAS2LE1IS, NULL, NULL), SYS_INSN_TO_DESC(TLBI_ALLE2IS, handle_alle2is, NULL), SYS_INSN_TO_DESC(TLBI_VAE2IS, handle_vae2, NULL), - SYS_INSN_TO_DESC(TLBI_ALLE1IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE1IS, handle_alle1is, NULL), SYS_INSN_TO_DESC(TLBI_VALE2IS, handle_vae2, NULL), SYS_INSN_TO_DESC(TLBI_VMALLS12E1IS, NULL, NULL), SYS_INSN_TO_DESC(TLBI_IPAS2E1, NULL, NULL), SYS_INSN_TO_DESC(TLBI_IPAS2LE1, NULL, NULL), SYS_INSN_TO_DESC(TLBI_ALLE2, handle_alle2, NULL), SYS_INSN_TO_DESC(TLBI_VAE2, handle_vae2, NULL), - SYS_INSN_TO_DESC(TLBI_ALLE1, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE1, handle_alle1is, NULL), SYS_INSN_TO_DESC(TLBI_VALE2, handle_vae2, NULL), SYS_INSN_TO_DESC(TLBI_VMALLS12E1, NULL, NULL), };