From patchwork Thu Oct 5 10:53:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wanpeng Li X-Patchwork-Id: 9986807 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AD1016029B for ; Thu, 5 Oct 2017 10:54:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B72C528C5E for ; Thu, 5 Oct 2017 10:54:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABAB928C64; Thu, 5 Oct 2017 10:54:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46AC028C5E for ; Thu, 5 Oct 2017 10:54:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752323AbdJEKy0 (ORCPT ); Thu, 5 Oct 2017 06:54:26 -0400 Received: from mail-qk0-f194.google.com ([209.85.220.194]:36537 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752195AbdJEKyV (ORCPT ); Thu, 5 Oct 2017 06:54:21 -0400 Received: by mail-qk0-f194.google.com with SMTP id z14so9731115qkg.3; Thu, 05 Oct 2017 03:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AS7bN168HjhI1REmDoI3iMzTHskRPF/qZ37qLIp3YGg=; b=lGYvdcHWdkeH66woKypjBtvcq9wpGyXxlwrLgoFr9t/M8P/LjvFXi0r2m0hcf+AfGt LkgQJzzueASYekw8Q4VA8m375wccdgt1tkY5MHiORrBAsth8t+fqoLB/Xbh9Sg2zutoh BEcKseLT9jkxQr72lYX/HpFrvsfBKonOwwrQ0SzkpTZKQiGGky/+5ZmqFuaBWCK+qBvh UbWtPR6VyvKZsvfTqp0ejD+z8+TpHlyXfgm8a23HD9PhluZqkDDZ1fToEaqOeljXY2dq v7wHF+8MutyC1yw+XP8yuJQAz6uEG3EGe6a4zUimZN6XQambXciudwS8+e7qwpbifgTv uwHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AS7bN168HjhI1REmDoI3iMzTHskRPF/qZ37qLIp3YGg=; b=NfJFLyeohGGGanieOqcLwrV5pppC4CKawsXTRmmau1b9aBFJmViRjp3ZbxraTUoXZr UFCga5v1CWqvkhTSBRQGP2KWHBOvK2A5ujUtSSsEIDqgE0m3kEBF45+7FhvObhKPOd4p xKW7af7RBFmHYOQ6Y4fbHIFcPWTRrd5X/7hypwUZQYwxP83Q/Cqk7iFVMgbFIvEawCgB T56ywPcEDlsAe8guJNCYquQjSWo2zaAoG9nzqShjoVFrbt+h7IkYHwL0CskniFCW8/Pw LvtQosZyJ8z6T2r5hXbqn0rsXB/WD1WHT86ihLdOWSRBv8Z4aG7EicU33DbtC6YLHBYS MrOA== X-Gm-Message-State: AMCzsaW8M12A6P2pe0Cipprs+4sGIQ52FM2xyu3xmurPzzTmZLJFHIKa Tx673FAMx0nIup+KEH/OyPFlu7Gi X-Google-Smtp-Source: AOwi7QDKrx1w6l+CHcEUfc9dNGq2YX5dBFzYrL+q4RHuzTVHDx6M1KlfJGCOi/7NHv3gKL2z9iZa6g== X-Received: by 10.55.183.134 with SMTP id h128mr11088562qkf.258.1507200860135; Thu, 05 Oct 2017 03:54:20 -0700 (PDT) Received: from localhost ([67.205.145.118]) by smtp.gmail.com with ESMTPSA id n45sm6391351qtf.51.2017.10.05.03.54.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 03:54:19 -0700 (PDT) From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wanpeng Li Subject: [PATCH v3 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer Date: Thu, 5 Oct 2017 03:53:53 -0700 Message-Id: <1507200833-20434-4-git-send-email-wanpeng.li@hotmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507200833-20434-1-git-send-email-wanpeng.li@hotmail.com> References: <1507200833-20434-1-git-send-email-wanpeng.li@hotmail.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wanpeng Li The description in the Intel SDM of how the divide configuration register is used: "The APIC timer frequency will be the processor's bus clock or core crystal clock frequency divided by the value specified in the divide configuration register." Observation of baremetal shown that when the TDCR is change, the TMCCT does not change or make a big jump in value, but the rate at which it count down change. The patch update the emulation to APIC timer to so that a change to the divide configuration would be reflected in the value of the counter and when the next interrupt is triggered. Cc: Paolo Bonzini Cc: Radim Krčmář Signed-off-by: Wanpeng Li --- arch/x86/kvm/lapic.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index df31048..5a3d6ba 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1436,7 +1436,7 @@ static void start_sw_period(struct kvm_lapic *apic) HRTIMER_MODE_ABS_PINNED); } -static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) +static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update, uint32_t old_divisor) { ktime_t now, remaining; u64 tscl = rdtsc(), delta; @@ -1444,7 +1444,7 @@ static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) /* Calculate the next time the timer should trigger an interrupt */ now = ktime_get(); apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) - * APIC_BUS_CYCLE_NS * apic->divide_count; + * APIC_BUS_CYCLE_NS * old_divisor; if (!apic->lapic_timer.period) return false; @@ -1489,6 +1489,12 @@ static bool set_target_expiration(struct kvm_lapic *apic, bool timer_update) if (!delta) return false; + if (apic->divide_count != old_divisor) { + apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) + * APIC_BUS_CYCLE_NS * apic->divide_count; + delta = delta * apic->divide_count / old_divisor; + } + apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + nsec_to_cycles(apic->vcpu, delta); apic->lapic_timer.target_expiration = ktime_add_ns(now, delta); @@ -1628,12 +1634,13 @@ void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) restart_apic_timer(apic); } -static void start_apic_timer(struct kvm_lapic *apic, bool timer_update) +static void start_apic_timer(struct kvm_lapic *apic, bool timer_update, + uint32_t old_divisor) { atomic_set(&apic->lapic_timer.pending, 0); if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) - && !set_target_expiration(apic, timer_update)) + && !set_target_expiration(apic, timer_update, old_divisor)) return; restart_apic_timer(apic); @@ -1746,7 +1753,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); kvm_lapic_set_reg(apic, APIC_LVTT, val); if (apic_update_lvtt(apic) && !apic_lvtt_tscdeadline(apic)) - start_apic_timer(apic, true); + start_apic_timer(apic, true, apic->divide_count); break; case APIC_TMICT: @@ -1755,16 +1762,20 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) hrtimer_cancel(&apic->lapic_timer.timer); kvm_lapic_set_reg(apic, APIC_TMICT, val); - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); break; - case APIC_TDCR: + case APIC_TDCR: { + uint32_t current_divisor = apic->divide_count; + if (val & 4) apic_debug("KVM_WRITE:TDCR %x\n", val); kvm_lapic_set_reg(apic, APIC_TDCR, val); update_divide_count(apic); + hrtimer_cancel(&apic->lapic_timer.timer); + start_apic_timer(apic, true, current_divisor); break; - + } case APIC_ESR: if (apic_x2apic_mode(apic) && val != 0) { apic_debug("KVM_WRITE:ESR not zero %x\n", val); @@ -1889,7 +1900,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) hrtimer_cancel(&apic->lapic_timer.timer); apic->lapic_timer.tscdeadline = data; - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); } void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) @@ -2255,7 +2266,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) apic_update_lvtt(apic); apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); update_divide_count(apic); - start_apic_timer(apic, false); + start_apic_timer(apic, false, apic->divide_count); apic->irr_pending = true; apic->isr_count = vcpu->arch.apicv_active ? 1 : count_vectors(apic->regs + APIC_ISR);