From patchwork Fri Oct 6 14:01:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wanpeng Li X-Patchwork-Id: 9989539 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BC8C060247 for ; Fri, 6 Oct 2017 14:02:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A67828B2B for ; Fri, 6 Oct 2017 14:02:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CE7828BC3; Fri, 6 Oct 2017 14:02:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4184A28B2B for ; Fri, 6 Oct 2017 14:02:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751540AbdJFOBq (ORCPT ); Fri, 6 Oct 2017 10:01:46 -0400 Received: from mail-qk0-f194.google.com ([209.85.220.194]:33839 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751459AbdJFOBp (ORCPT ); Fri, 6 Oct 2017 10:01:45 -0400 Received: by mail-qk0-f194.google.com with SMTP id b124so9356776qke.1; Fri, 06 Oct 2017 07:01:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=OA+EvfW76t7syLaMstm5Vqwk/jAlaBEb2CCSfJ+E3iE=; b=IiA9TL8eBDMgw5CJXLzvypZnS+T1qELXpaQaljSg2VTFMAxifmzVCJ3OFaDE9bXqz/ R5LOG/9CKEg4IYwSk+barknPQbkbRdSU0uBJ55NQC3S9Q6WwNkmEFhp2oxogk7EKcxmB DXJbx0aENOIj0GzedabUi8rzJBwnn5JZkqg1LgehRw1BOS9EmjoXzYSbN/SrFE3ER3Nw A4ASZGmv36ipjkwrjAtYYz3ULOQg6f/ZdRbXVtBpRiyZrJQaXKOZTDGkf7VtJT+EQcTE y36mnUgIdp4LYxAX0BbT8ARAZP647kgBcypYevGyivaj1KRUhhkSPtu/RsGPnIp/By6Q dO/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=OA+EvfW76t7syLaMstm5Vqwk/jAlaBEb2CCSfJ+E3iE=; b=ouXjnPta+6nOT8HG8L/JsHBmqIR2jqRab2XDRT8+dwRZFDvZ95qAc3C4Cwd6wtHvP9 TmPfY1GroJK3q/h2fAXbRr7jbnNOpkFrZurqM71wWhAjqGzMNWVUZJwt1WsXs7+cbCLz 6Q6KptTojcZIVp451HJRAuxbGHHC6N6RhuYWbZs859sFaRKU6DOkzyKeTks/OUQQx760 FCT6t6iUw4rsynwkfVxU6d0fQdKgZm5R8hV9AcpoePBxxyYpChCuE10J8zB0d+lzZwkQ 91rpDoFSACWVg74woZIUznVWQnh+kDD1OrwMtDnru6MVqZnPo76xD/msi44A6wWTqA4v FCuQ== X-Gm-Message-State: AMCzsaXvkaiA3ntPe2aCZ4+i6v2IS1hVFhp5V1boc9l8ZcFm18ugFO8J Mxyt9bZT7P9rup7w4V+6bJ/PiAKa X-Google-Smtp-Source: AOwi7QCn4qpV696MwHhFjYnwzv+PdA60gZISgAMP+NjZ0P2iEpOwTmvvCsDTWq0YCFRwxR2R3+BGTg== X-Received: by 10.55.65.75 with SMTP id o72mr16368828qka.249.1507298504705; Fri, 06 Oct 2017 07:01:44 -0700 (PDT) Received: from localhost ([67.205.145.118]) by smtp.gmail.com with ESMTPSA id u54sm968752qtj.44.2017.10.06.07.01.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 07:01:43 -0700 (PDT) From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wanpeng Li Subject: [PATCH v7] KVM: LAPIC: Apply change to TDCR right away to the timer Date: Fri, 6 Oct 2017 07:01:32 -0700 Message-Id: <1507298492-8300-1-git-send-email-wanpeng.li@hotmail.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wanpeng Li The description in the Intel SDM of how the divide configuration register is used: "The APIC timer frequency will be the processor's bus clock or core crystal clock frequency divided by the value specified in the divide configuration register." Observation of baremetal shown that when the TDCR is change, the TMCCT does not change or make a big jump in value, but the rate at which it count down change. The patch update the emulation to APIC timer to so that a change to the divide configuration would be reflected in the value of the counter and when the next interrupt is triggered. Cc: Paolo Bonzini Cc: Radim Krčmář Signed-off-by: Wanpeng Li --- v6 -> v7: * always modify the period * added precision and maybe performance * doing restart_apic_timer() unconditionally arch/x86/kvm/lapic.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 14f63b3..bf047e3 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1458,6 +1458,35 @@ static void start_sw_period(struct kvm_lapic *apic) HRTIMER_MODE_ABS_PINNED); } +static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) +{ + ktime_t now, remaining; + u64 delta; + + apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) + * APIC_BUS_CYCLE_NS * apic->divide_count; + + if (!apic->lapic_timer.period) + return; + + now = ktime_get(); + remaining = ktime_sub(apic->lapic_timer.target_expiration, now); + if (ktime_to_ns(remaining) < 0) + remaining = 0; + delta = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); + + if (!delta) + return; + + delta = delta * apic->divide_count / old_divisor; + + limit_periodic_timer_frequency(apic); + + apic->lapic_timer.tscdeadline += nsec_to_cycles(apic->vcpu, delta) - + nsec_to_cycles(apic->vcpu, remaining); + apic->lapic_timer.target_expiration = ktime_add_ns(now, delta); +} + static bool set_target_expiration(struct kvm_lapic *apic) { ktime_t now; @@ -1750,13 +1779,20 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) start_apic_timer(apic); break; - case APIC_TDCR: + case APIC_TDCR: { + uint32_t old_divisor = apic->divide_count; + if (val & 4) apic_debug("KVM_WRITE:TDCR %x\n", val); kvm_lapic_set_reg(apic, APIC_TDCR, val); update_divide_count(apic); + if (apic->divide_count != old_divisor) { + hrtimer_cancel(&apic->lapic_timer.timer); + update_target_expiration(apic, old_divisor); + restart_apic_timer(apic); + } break; - + } case APIC_ESR: if (apic_x2apic_mode(apic) && val != 0) { apic_debug("KVM_WRITE:ESR not zero %x\n", val);