From patchwork Thu Jan 11 10:11:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: simon X-Patchwork-Id: 10157731 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 328F5602B3 for ; Thu, 11 Jan 2018 10:12:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32EA5205A4 for ; Thu, 11 Jan 2018 10:12:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2785328402; Thu, 11 Jan 2018 10:12:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF4D9205A4 for ; Thu, 11 Jan 2018 10:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933242AbeAKKMR (ORCPT ); Thu, 11 Jan 2018 05:12:17 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:40886 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933227AbeAKKMP (ORCPT ); Thu, 11 Jan 2018 05:12:15 -0500 Received: by mail-pg0-f65.google.com with SMTP id q12so1863985pgt.7; Thu, 11 Jan 2018 02:12:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pNkUP1d4Pto6aqXZ6++37EGX0AOPSHUUOSr1SA1EmTU=; b=trZI2Lib5RmH4K+39OENBBu9vSHM/nB3frfu+lG1J72uUc1uFm1aHgAl4PMWEwCZwZ mZJ9PMaImZs3xtg0YhlYw8pWyANQvVLWkMv6LECNqtkRjpIsGt8GdrozHCBCutYgJbWv s2ve7qI62/nG//bHjXHlNU0PSfHD3J+RukHH4VoJPyUXzYx6iUQdNTD6PvOAd/ecOWwn C3rRWKP3m8NaTPh+m90s7v4o67MgL0OFLgbnu3mZaT2TSxVfASqF5zFk9sjRAp9BtyD4 hN/nD+M01xh/1YCPjGWRQ9wHqpXdHdJvyY42VnXMlGZ6wSvS/hLOzczfQVFsy8L+J92W +KdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pNkUP1d4Pto6aqXZ6++37EGX0AOPSHUUOSr1SA1EmTU=; b=YiL0QGjFBskNNRDXZDBprKh1mjTEtEnRTUuBf+keus3FeZvnTR57QiaoNk6nyWZ2GM 9lrutfEZCOFo45oTCd8mFJIzTfwh6rFSVC5OsUT5jitJbNiZfCg+vrKdKi3dG8cqpn3u lPpTzG+BRO9LWhKRyMsMckM3Kcd5fcLaiK+YVSty2Teb32+XOoJYEDnsTjs8nbSsaz4G WfwEjxPlefBhjFHfJAI3ZjAVpgl4wwregDAgBmFX+9leWW96BDkyoCkQ29WU/58msGU9 IKCNy+DvcnGcqAL/js7dCY2PbP03v5zE/fHOTqvPTfzu9H5c8f7MYl/g8GRGkdN7DAnZ ONnw== X-Gm-Message-State: AKGB3mJH+D2BeXNL3fNZfISb5aPJUKPQrmGsH0oG5sTD+x1o36XvXOzX 6ZYEHr5xIQG4FLoA2PMOrFQ= X-Google-Smtp-Source: ACJfBovAlz091BcNpUM/k1vAzZKWVYXEPkalb+GZhFT/oAzpoJyytKyYyDHQHYt+CkhJNhKtQNsVMQ== X-Received: by 10.98.6.130 with SMTP id 124mr19480713pfg.8.1515665535405; Thu, 11 Jan 2018 02:12:15 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:14 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros Date: Thu, 11 Jan 2018 18:11:20 +0800 Message-Id: <1515665499-31710-8-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/include/asm/reg.h | 21 ++++++++++++++++++++- arch/powerpc/platforms/powernv/copy-paste.h | 3 +-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b779f3c..6c293bc 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ @@ -237,8 +243,21 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_HV __MASK(TEXASR_HV_LG) +#define TEXASR_PR __MASK(TEXASR_PR_LG) +#define TEXASR_FS __MASK(TEXASR_FS_LG) +#define TEXASR_EX __MASK(TEXASR_EX_LG) +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098 diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..3fa62de 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h +++ b/arch/powerpc/platforms/powernv/copy-paste.h @@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include +#include -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: *