From patchwork Tue Jan 23 20:58:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Woodhouse X-Patchwork-Id: 10181061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 618366019D for ; Tue, 23 Jan 2018 20:58:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5114E287C9 for ; Tue, 23 Jan 2018 20:58:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 44CAC287ED; Tue, 23 Jan 2018 20:58:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91986287C9 for ; Tue, 23 Jan 2018 20:58:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932088AbeAWU6o (ORCPT ); Tue, 23 Jan 2018 15:58:44 -0500 Received: from twosheds.infradead.org ([90.155.92.209]:52830 "EHLO twosheds.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752640AbeAWU6m (ORCPT ); Tue, 23 Jan 2018 15:58:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=twosheds.20170209; h=Mime-Version:Date:Content-Type: References:In-Reply-To:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=pk3fUJGx9zD4L9Yos/+OyvKvt5tQcDSN3U9ro+KM0bs=; b=C0HVOUWYj7eqkmm71uyV+IcRm lIWp4AIn/t+dpuAQsLNbC07E0hddUcJgzvagi23Ru0DOwvQiVBsIyzzsJXHlKem8eqIuLsmXZq7a2 5+/2HMre/Rh5Ezn5sX+lfraFNV8DwHHgGKZ4WSd9IgyEr2I9mW62xaRDlsJGBytdvS+OQkC7rNr3U aCpsBt2fT/UHj4EHEDQTNcOHy2bO1Ho1lB8tSaxdWRaVTsjmBLsqPOEm74M09vBdKYWfRdRpXRIXD DguEUPASM8pfIQy5rG4GUfIgOUOIZ20/Ioq1Hm1yilAHv/j/yXgjbNwHCgAtyJeKyQKtBQD7M4ryO 9oMKsBPRg==; Received: from [2001:8b0:10b:1:5c5:5b94:948a:4d8a] by twosheds.infradead.org with esmtpsa (Exim 4.89 #1 (Red Hat Linux)) id 1ee5eO-0001KA-Cx; Tue, 23 Jan 2018 20:58:36 +0000 Message-ID: <1516741116.13558.11.camel@infradead.org> Subject: Re: [RFC 05/10] x86/speculation: Add basic IBRS support infrastructure From: David Woodhouse To: Thomas Gleixner , KarimAllah Ahmed Cc: linux-kernel@vger.kernel.org, Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Arjan van de Ven , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds , Masami Hiramatsu , Paolo Bonzini , Peter Zijlstra , Radim =?UTF-8?Q?Kr=C4=8Dm=C3=A1=C5=99?= , Tim Chen , Tom Lendacky , kvm@vger.kernel.org, x86@kernel.org In-Reply-To: References: <1516476182-5153-1-git-send-email-karahmed@amazon.de> <1516476182-5153-6-git-send-email-karahmed@amazon.de> Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAG1BMVEUHBwcUFBQpKSlGRkZhYWF9fX2Xl5eysrLMzMxFF+rXAAACaElEQVQ4y21UQXbbIBQE9wJALmAg6ToWON22FrhZthHgbvssUPathC7QWMful2JHSmtWwGg+zPxBCE0DU4QoJQgRgsg4w2gJjBNE8PjFBZgnQMBs+uZ1NQNQjZO3BV4AGDFC0f+l4DBG0VUAM4yv7SO8IgRdHXQ+A78HKL5OAeCfNQV5cHX8DsBUyIJKtYbt98BKaGNCKjfgFVkqYVLbkHKsRsbSCSa0T6npIqLrpRBgQKHUpQmgs9eEKaiUcooE8WWfCGVnBiUcn1uF2XhbfmN9apKnmMP2K4kizKkQWxuaVNOpU2cACIyxO1Po8ETHcXEDMVnozcejkAYA9iaD4pU0ZvNQ8VurNnTuFAYVtuIPUZW25PjDIjQAlGyffIiRQxoWAZBmJ0LTdW2Nyc0iP3DqRhxizvGJkBWZmyFVyZkddWzmBoIBVMpCCJ1CFzl98xav4VJKSSD45KbUT75ixikTphDSRh8+Uz7JLgUTAgAFwzqzjxc/nDY7WUApqY0OMdTwCKZSXplSKkgIRCHElCp8ZnhnKqXuwcNbk1L0VXE+I9alUXoHlLHl3mv7/dWQlJwtjREC7mu9L/U2jQyMUuO2EDS4q9Kl2ddm232bxIE5pjJuVwiljNn/Cfv25/T0cu5cZbwHGVq7h/zp0B4n3S99V/utD+Uo8BiGx9xCsOAV5z7/tjo4Z4z1Lvb90KZ7eFOoOeXOukqF2seo234YYuaQPpRP+cVZU5adT1Edun5Iz3z8fTz3+eSDh0Ip1c7zx1MaijGzTd/3MbRuBHz8cvcVgCMBRpOHvgu59WDhoat+nIZm+LWm9C/aaaGq5DCP9QAAAABJRU5ErkJggg== Date: Tue, 23 Jan 2018 20:58:36 +0000 Mime-Version: 1.0 X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sun, 2018-01-21 at 15:31 +0100, Thomas Gleixner wrote: > >  > > XX: Do we want a microcode blacklist? > > Oh yes, we want a microcode blacklist. Ideally we refuse to load the > affected microcode in the first place and if its already loaded then at > least avoid to use the borked features. > > PR texts promising that Intel is committed to transparency in this matter > are not sufficient. Intel, please provide the facts, i.e. a proper list of > micro codes and affected SKUs, ASAP. They've finally published one, at https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf For shits and giggles, you can compare it with the one at https://kb.vmware.com/s/article/52345 Intel's seems to be a bit rushed. For example for Broadwell-EX 406F1 they say "0x25, 0x23" are bad, but VMware's list says 0x0B000025 and I have a CPU with 0x0B0000xx. So I've "corrected" their numbers in attempt at a blacklist patch accordingly, and likewise for some Skylake SKUs. But there are others in Intel's list that I can't easily proofread for them right now. Am I missing something? diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b720dacac051..52855d1a4f9a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -102,6 +102,57 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)   ELF_HWCAP2 |= HWCAP2_RING3MWAIT;  }   +/* + * Early microcode releases for the Spectre v2 mitigation were broken: + * https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf + * VMware also has a list at https://kb.vmware.com/s/article/52345 + */ +struct sku_microcode { + u8 model; + u8 stepping; + u32 microcode; +}; +static const struct sku_microcode spectre_bad_microcodes[] = { + { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 }, + { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 }, + { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 }, + { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 }, + { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 }, + { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003C }, + { INTEL_FAM6_SKYLAKE_MOBILE, 0x03, 0x000000C2 }, + { INTEL_FAM6_SKYLAKE_DESKTOP, 0x03, 0x000000C2 }, + { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 }, + { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x0000001B }, + { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 }, + { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 }, + { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 }, + { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, + { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, + { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, + { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 }, + { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 }, + { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x7000011 }, + { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x0000001B }, + /* For 406F1 Intel says "0x25, 0x23" while VMware says 0x0B000025 +  * and a real CPU has a firmware in the 0x0B0000xx range. So: */ + { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, + { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 }, + { INTEL_FAM6_SKYLAKE_X, 0x03, 0x100013e }, + { INTEL_FAM6_SKYLAKE_X, 0x04, 0x200003c }, +}; + +static int bad_spectre_microcode(struct cpuinfo_x86 *c) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { + if (c->x86_model == spectre_bad_microcodes[i].model && +     c->x86_mask == spectre_bad_microcodes[i].stepping) + return (c->microcode <= spectre_bad_microcodes[i].microcode); + } + return 0; +} +  static void early_init_intel(struct cpuinfo_x86 *c)  {   u64 misc_enable; @@ -122,6 +173,18 @@ static void early_init_intel(struct cpuinfo_x86 *c)   if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))   c->microcode = intel_get_microcode_revision();   + if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || +      cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) || +      cpu_has(c, X86_FEATURE_AMD_PRED_CMD) || +      cpu_has(c, X86_FEATURE_AMD_STIBP)) && bad_spectre_microcode(c)) { + pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL\n"); + clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL); + clear_cpu_cap(c, X86_FEATURE_STIBP); + clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL); + clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD); + clear_cpu_cap(c, X86_FEATURE_AMD_STIBP); + } +   /*    * Atom erratum AAE44/AAF40/AAG38/AAH41:    *