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Sat, 24 Feb 2018 02:30:47 +0000 From: Babu Moger To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Cc: mtosatti@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org, pixo@polepetko.eu, Gary.Hook@amd.com, babu.moger@amd.com Subject: [PATCH v2 2/5] target/i386: Populate AMD Processor Cache Information Date: Fri, 23 Feb 2018 21:30:22 -0500 Message-Id: <1519439425-27883-3-git-send-email-babu.moger@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1519439425-27883-1-git-send-email-babu.moger@amd.com> References: <1519439425-27883-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR06CA0061.namprd06.prod.outlook.com (2603:10b6:3:37::23) To MWHPR12MB1776.namprd12.prod.outlook.com (2603:10b6:300:113::7) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 2edf8421-28f3-4345-89ff-08d57b2e9d9a X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(4534165)(4627221)(201703031133081)(201702281549075)(5600026)(4604075)(2017052603307)(7153060)(7193020); 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MWHPR12MB1776; 20:c/OvsCc9h1kbAsDb7NgiEQGAZD2PDK5pk6zSvQfiDvSgrcM+g6L8qlyb4QE0Z9pe0AIHEA+Yf8ldFxTqD73WJqSGiry4qV7QBqVbhdsQRT4vwPmmsapjfwwNuQTi/s60YScg+lWwNdErCjr/CGV2Cz27s3LFwmsov0lgmkQ+BN3JFJxgbQacmcZ2rbjNZfrbM83LUOnZU2MgJVYh1T5UozthqvfyBXT5gxVwrXZsUC+UVvIW4ywz8ajnHfWW0apx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2018 02:30:47.9562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2edf8421-28f3-4345-89ff-08d57b2e9d9a X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1776 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stanislav Lanci Adds information about cache size and topology from cpuid 0x8000001D leaf for different cache types on AMD processors. Signed-off-by: Stanislav Lanci Signed-off-by: Babu Moger --- target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ target/i386/kvm.c | 29 ++++++++++++++++++--- 2 files changed, 102 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5e431e..a5a480e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -118,6 +118,7 @@ #define L1I_LINE_SIZE 64 #define L1I_ASSOCIATIVITY 8 #define L1I_SETS 64 +#define L1I_SETS_AMD 256 #define L1I_PARTITIONS 1 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */ #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B @@ -129,7 +130,9 @@ /* Level 2 unified cache: */ #define L2_LINE_SIZE 64 #define L2_ASSOCIATIVITY 16 +#define L2_ASSOCIATIVITY_AMD 8 #define L2_SETS 4096 +#define L2_SETS_AMD 1024 #define L2_PARTITIONS 1 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */ /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -146,6 +149,7 @@ #define L3_N_LINE_SIZE 64 #define L3_N_ASSOCIATIVITY 16 #define L3_N_SETS 16384 +#define L3_N_SETS_AMD 8192 #define L3_N_PARTITIONS 1 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B #define L3_N_LINES_PER_TAG 1 @@ -3590,6 +3594,78 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = 0; } break; + case 0x8000001D: /* AMD TOPOEXT cache info */ + if (cpu->cache_info_passthrough) { + host_cpuid(index, count, eax, ebx, ecx, edx); + break; + } else if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) { + *eax = 0; + switch (count) { + case 0: /* L1 dcache info */ + *eax |= CPUID_4_TYPE_DCACHE | \ + CPUID_4_LEVEL(1) | \ + CPUID_4_SELF_INIT_LEVEL | \ + ((cs->nr_threads - 1) << 14); + *ebx = (L1D_LINE_SIZE - 1) | \ + ((L1D_PARTITIONS - 1) << 12) | \ + ((L1D_ASSOCIATIVITY - 1) << 22); + *ecx = L1D_SETS - 1; + *edx = 0; + break; + case 1: /* L1 icache info */ + *eax |= CPUID_4_TYPE_ICACHE | \ + CPUID_4_LEVEL(1) | \ + CPUID_4_SELF_INIT_LEVEL | \ + ((cs->nr_threads - 1) << 14); + *ebx = (L1I_LINE_SIZE - 1) | \ + ((L1I_PARTITIONS - 1) << 12) | \ + ((L1I_ASSOCIATIVITY_AMD - 1) << 22); + *ecx = L1I_SETS_AMD - 1; + *edx = 0; + break; + case 2: /* L2 cache info */ + *eax |= CPUID_4_TYPE_UNIFIED | \ + CPUID_4_LEVEL(2) | \ + CPUID_4_SELF_INIT_LEVEL | \ + ((cs->nr_threads - 1) << 14); + *ebx = (L2_LINE_SIZE - 1) | \ + ((L2_PARTITIONS - 1) << 12) | \ + ((L2_ASSOCIATIVITY_AMD - 1) << 22); + *ecx = L2_SETS_AMD - 1; + *edx = CPUID_4_INCLUSIVE; + break; + case 3: /* L3 cache info */ + if (!cpu->enable_l3_cache) { + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; + } + *eax |= CPUID_4_TYPE_UNIFIED | \ + CPUID_4_LEVEL(3) | \ + CPUID_4_SELF_INIT_LEVEL | \ + ((cs->nr_cores * cs->nr_threads - 1) << 14); + *ebx = (L3_N_LINE_SIZE - 1) | \ + ((L3_N_PARTITIONS - 1) << 12) | \ + ((L3_N_ASSOCIATIVITY - 1) << 22); + *ecx = L3_N_SETS_AMD - 1; + *edx = CPUID_4_NO_INVD_SHARING; + break; + default: /* end of info */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; + } + } else { + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + } + break; case 0xC0000000: *eax = env->cpuid_xlevel2; *ebx = 0; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 85856b6..8adf7d1 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -909,9 +909,32 @@ int kvm_arch_init_vcpu(CPUState *cs) } c = &cpuid_data.entries[cpuid_i++]; - c->function = i; - c->flags = 0; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + switch (i) { + case 0x8000001d: + /* Query for all AMD cache information leaves */ + for (j = 0; ; j++) { + c->function = i; + c->flags = KVM_CPUID_FLAG_SIGNIFICANT_INDEX; + c->index = j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); + + if (c->eax == 0) { + break; + } + if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c = &cpuid_data.entries[cpuid_i++]; + } + break; + default: + c->function = i; + c->flags = 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + break; + } } /* Call Centaur's CPUID instructions they are supported. */