| Message ID | 1520492887-8021-1-git-send-email-shunyong.yang@hxt-semitech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Thanks for fixing it. Patch looks good to me. +Alex to pull this patch. Reviewed by: Kirti Wankhede <kwankhede@nvidia.com> Thanks, Kirti On 3/8/2018 12:38 PM, Shunyong Yang wrote: > When FIFO mode is enabled, the receive data available interrupt > (UART_IIR_RDI in code) should be triggered when the number of data > in FIFO is equal or larger than interrupt trigger level. > > This patch changes the trigger level check to ensure multiple bytes > received from upper layer can trigger RDI interrupt correctly. > > Cc: Joey Zheng <yu.zheng@hxt-semitech.com> > Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> > --- > samples/vfio-mdev/mtty.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c > index 09f255bdf3ac..7abb79d8313d 100644 > --- a/samples/vfio-mdev/mtty.c > +++ b/samples/vfio-mdev/mtty.c > @@ -534,7 +534,7 @@ static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state, > > /* Interrupt priority 2: Fifo trigger level reached */ > if ((ier & UART_IER_RDI) && > - (mdev_state->s[index].rxtx.count == > + (mdev_state->s[index].rxtx.count >= > mdev_state->s[index].intr_trigger_level)) > *buf |= UART_IIR_RDI; > >
Hi, Alex, Gentle ping. Could you please help to pull this patch? It's a small fix and Kirti has reviewed. Thanks. Shunyong. On Fri, 2018-03-09 at 11:36 +0530, Kirti Wankhede wrote: > Thanks for fixing it. > Patch looks good to me. > +Alex to pull this patch. > > Reviewed by: Kirti Wankhede <kwankhede@nvidia.com> > > Thanks, > Kirti > > On 3/8/2018 12:38 PM, Shunyong Yang wrote: > > > > When FIFO mode is enabled, the receive data available interrupt > > (UART_IIR_RDI in code) should be triggered when the number of data > > in FIFO is equal or larger than interrupt trigger level. > > > > This patch changes the trigger level check to ensure multiple bytes > > received from upper layer can trigger RDI interrupt correctly. > > > > Cc: Joey Zheng <yu.zheng@hxt-semitech.com> > > Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> > > --- > > samples/vfio-mdev/mtty.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c > > index 09f255bdf3ac..7abb79d8313d 100644 > > --- a/samples/vfio-mdev/mtty.c > > +++ b/samples/vfio-mdev/mtty.c > > @@ -534,7 +534,7 @@ static void handle_bar_read(unsigned int index, > > struct mdev_state *mdev_state, > > > > /* Interrupt priority 2: Fifo trigger level > > reached */ > > if ((ier & UART_IER_RDI) && > > - (mdev_state->s[index].rxtx.count == > > + (mdev_state->s[index].rxtx.count >= > > mdev_state->s[index].intr_trigger_level)) > > *buf |= UART_IIR_RDI; > > > >
On Fri, 9 Mar 2018 11:36:05 +0530 Kirti Wankhede <kwankhede@nvidia.com> wrote: > Thanks for fixing it. > Patch looks good to me. > +Alex to pull this patch. > > Reviewed by: Kirti Wankhede <kwankhede@nvidia.com> Applied to vfio next branch for v4.17 with Kirti's Rb. Thanks, Alex > On 3/8/2018 12:38 PM, Shunyong Yang wrote: > > When FIFO mode is enabled, the receive data available interrupt > > (UART_IIR_RDI in code) should be triggered when the number of data > > in FIFO is equal or larger than interrupt trigger level. > > > > This patch changes the trigger level check to ensure multiple bytes > > received from upper layer can trigger RDI interrupt correctly. > > > > Cc: Joey Zheng <yu.zheng@hxt-semitech.com> > > Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> > > --- > > samples/vfio-mdev/mtty.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c > > index 09f255bdf3ac..7abb79d8313d 100644 > > --- a/samples/vfio-mdev/mtty.c > > +++ b/samples/vfio-mdev/mtty.c > > @@ -534,7 +534,7 @@ static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state, > > > > /* Interrupt priority 2: Fifo trigger level reached */ > > if ((ier & UART_IER_RDI) && > > - (mdev_state->s[index].rxtx.count == > > + (mdev_state->s[index].rxtx.count >= > > mdev_state->s[index].intr_trigger_level)) > > *buf |= UART_IIR_RDI; > > > >
diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c index 09f255bdf3ac..7abb79d8313d 100644 --- a/samples/vfio-mdev/mtty.c +++ b/samples/vfio-mdev/mtty.c @@ -534,7 +534,7 @@ static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state, /* Interrupt priority 2: Fifo trigger level reached */ if ((ier & UART_IER_RDI) && - (mdev_state->s[index].rxtx.count == + (mdev_state->s[index].rxtx.count >= mdev_state->s[index].intr_trigger_level)) *buf |= UART_IIR_RDI;
When FIFO mode is enabled, the receive data available interrupt (UART_IIR_RDI in code) should be triggered when the number of data in FIFO is equal or larger than interrupt trigger level. This patch changes the trigger level check to ensure multiple bytes received from upper layer can trigger RDI interrupt correctly. Cc: Joey Zheng <yu.zheng@hxt-semitech.com> Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> --- samples/vfio-mdev/mtty.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)