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Tue, 27 Mar 2018 21:31:21 +0000 From: Babu Moger To: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, kash@tripleback.net, babu.moger@amd.com Subject: [PATCH v5 2/9] i386: Add cache information in X86CPUDefinition Date: Tue, 27 Mar 2018 17:31:04 -0400 Message-Id: <1522186271-27743-3-git-send-email-babu.moger@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1522186271-27743-1-git-send-email-babu.moger@amd.com> References: <1522186271-27743-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: CY4PR04CA0039.namprd04.prod.outlook.com (2603:10b6:903:c6::25) To DM5PR12MB1771.namprd12.prod.outlook.com (2603:10b6:3:113::8) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0d4be97a-a616-4a33-8aaa-08d5942a15ad X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020); 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Signed-off-by: Babu Moger --- target/i386/cpu.c | 4 ++++ target/i386/cpu.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index da59dc4..eec4a97 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1102,6 +1102,7 @@ struct X86CPUDefinition { int stepping; FeatureWordArray features; const char *model_id; + CPUCaches cache_info; }; static X86CPUDefinition builtin_x86_defs[] = { @@ -3239,6 +3240,9 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp) env->features[w] = def->features[w]; } + /* Load Cache information from the X86CPUDefinition */ + memcpy(&env->cache_info, &def->cache_info, sizeof(CPUCaches)); + /* Special cases not set in the X86CPUDefinition structs: */ /* TODO: in-kernel irqchip for hvf */ if (kvm_enabled()) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 79d5ccf..806c34b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1096,6 +1096,13 @@ typedef struct CPUCacheInfo { } CPUCacheInfo; +typedef struct CPUCaches { + bool valid; + CPUCacheInfo l1d_cache; + CPUCacheInfo l1i_cache; + CPUCacheInfo l2_cache; + CPUCacheInfo l3_cache; +} CPUCaches; typedef struct CPUX86State { /* standard registers */ @@ -1282,6 +1289,7 @@ typedef struct CPUX86State { /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; + CPUCaches cache_info; /* MTRRs */ uint64_t mtrr_fixed[11];