diff mbox

KVM: x86: remove double definitions of msr tsc deadline

Message ID 1522233405-6221-1-git-send-email-zhenwei.pi@youruncloud.com (mailing list archive)
State New, archived
Headers show

Commit Message

ZhenweiPi March 28, 2018, 10:36 a.m. UTC 
Both MSR_IA32_TSCDEADLINE and MSR_IA32_TSC_DEADLINE
define 0x000006e0.
Intel SDM uses MSR_IA32_TSC_DEADLINE, so remove
MSR_IA32_TSCDEADLINE.

Signed-off-by: zhenwei.pi <zhenwei.pi@youruncloud.com>
---
 arch/x86/include/asm/msr-index.h | 2 --
 arch/x86/kvm/x86.c               | 6 +++---
 2 files changed, 3 insertions(+), 5 deletions(-)

Comments

Greg KH March 28, 2018, 10:44 a.m. UTC | #1 
On Wed, Mar 28, 2018 at 06:36:45PM +0800, zhenwei.pi wrote:
> Both MSR_IA32_TSCDEADLINE and MSR_IA32_TSC_DEADLINE
> define 0x000006e0.
> Intel SDM uses MSR_IA32_TSC_DEADLINE, so remove
> MSR_IA32_TSCDEADLINE.
> 
> Signed-off-by: zhenwei.pi <zhenwei.pi@youruncloud.com>

We need a "real" name here, I doubt you sign your documents with a "."
in them :)

thanks,

greg k-h
diff mbox

Patch

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index c9084de..fac31d1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -463,8 +463,6 @@ 
 #define MSR_IA32_APICBASE_ENABLE	(1<<11)
 #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
 
-#define MSR_IA32_TSCDEADLINE		0x000006e0
-
 #define MSR_IA32_UCODE_WRITE		0x00000079
 #define MSR_IA32_UCODE_REV		0x0000008b
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 18b5ca7..01540dd 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1036,7 +1036,7 @@  static u32 emulated_msrs[] = {
 	MSR_KVM_PV_EOI_EN,
 
 	MSR_IA32_TSC_ADJUST,
-	MSR_IA32_TSCDEADLINE,
+	MSR_IA32_TSC_DEADLINE,
 	MSR_IA32_MISC_ENABLE,
 	MSR_IA32_MCG_STATUS,
 	MSR_IA32_MCG_CTL,
@@ -2310,7 +2310,7 @@  int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		return kvm_set_apic_base(vcpu, msr_info);
 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
 		return kvm_x2apic_msr_write(vcpu, msr, data);
-	case MSR_IA32_TSCDEADLINE:
+	case MSR_IA32_TSC_DEADLINE:
 		kvm_set_lapic_tscdeadline_msr(vcpu, data);
 		break;
 	case MSR_IA32_TSC_ADJUST:
@@ -2595,7 +2595,7 @@  int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
 		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
 		break;
-	case MSR_IA32_TSCDEADLINE:
+	case MSR_IA32_TSC_DEADLINE:
 		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
 		break;
 	case MSR_IA32_TSC_ADJUST: