From patchwork Tue May 22 02:51:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 10413779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 60639601F9 for ; Mon, 21 May 2018 01:13:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4143228741 for ; Mon, 21 May 2018 01:13:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 357D52874F; Mon, 21 May 2018 01:13:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_24_48, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EE5D28741 for ; Mon, 21 May 2018 01:13:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751547AbeEUBNO (ORCPT ); Sun, 20 May 2018 21:13:14 -0400 Received: from mga18.intel.com ([134.134.136.126]:17424 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751451AbeEUBNN (ORCPT ); Sun, 20 May 2018 21:13:13 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 May 2018 18:13:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,425,1520924400"; d="scan'208";a="42820403" Received: from dst.sh.intel.com ([10.239.48.156]) by orsmga008.jf.intel.com with ESMTP; 20 May 2018 18:13:10 -0700 From: Jingqi Liu To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, wei.w.wang@intel.com, Jingqi Liu Subject: [PATCH] KVM: x86: Expose the split lock detection feature to guest VM Date: Tue, 22 May 2018 10:51:47 +0800 Message-Id: <1526957507-123937-1-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 1.8.3.1 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A new control bit(bit 29) in the TEST_CTL MSR will be introduced to enable detection of split locks. When bit 29 of the TEST_CTL(33H) MSR is set, the processor causes an #AC exception to be issued instead of suppressing LOCK on bus(during split lock access). A previous control bit (bit 31) in this MSR causes the processor to disable LOCK# assertion for split locked accesses when set. When bits 29 and 31 are both set, bit 29 takes precedence. The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf This patch has a dependency on https://lkml.org/lkml/2018/5/14/1157 Signed-off-by: Jingqi Liu --- arch/x86/kvm/vmx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 3f16965..07986e0 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -610,6 +610,8 @@ struct vcpu_vmx { u64 arch_capabilities; u64 spec_ctrl; + u64 guest_split_lock_ctrl; + u64 host_split_lock_ctrl; u32 vm_entry_controls_shadow; u32 vm_exit_controls_shadow; @@ -6013,6 +6015,8 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx) vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); + vmx->guest_split_lock_ctrl = 0; + if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); @@ -6062,6 +6066,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) vmx->rmode.vm86_active = 0; vmx->spec_ctrl = 0; + vmx->guest_split_lock_ctrl = 0; vcpu->arch.microcode_version = 0x100000000ULL; vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); @@ -9725,6 +9730,9 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) if (vmx->spec_ctrl) native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl); + vmx->host_split_lock_ctrl = native_read_msr(MSR_TEST_CTL); + native_wrmsrl(MSR_TEST_CTL, vmx->guest_split_lock_ctrl); + vmx->__launched = vmx->loaded_vmcs->launched; evmcs_rsp = static_branch_unlikely(&enable_evmcs) ? @@ -9874,6 +9882,9 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) if (vmx->spec_ctrl) native_wrmsrl(MSR_IA32_SPEC_CTRL, 0); + vmx->guest_split_lock_ctrl = native_read_msr(MSR_TEST_CTL); + native_wrmsrl(MSR_TEST_CTL, vmx->host_split_lock_ctrl); + /* Eliminate branch target predictions from guest mode */ vmexit_fill_RSB(); @@ -10037,6 +10048,8 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); + vmx_disable_intercept_for_msr(msr_bitmap, MSR_TEST_CTL, MSR_TYPE_RW); + vmx->msr_bitmap_mode = 0; vmx->loaded_vmcs = &vmx->vmcs01;