| Message ID | 1526964735-16566-12-git-send-email-luwei.kang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 22, 2018 at 12:52:14PM +0800, Luwei Kang wrote: > From: Chao Peng <chao.p.peng@linux.intel.com> > > Disable intercept Intel PT MSRs only when Intel PT is > enabled in guest. But MSR_IA32_RTIT_CTL will alway be > intercept. "I'd like to offer some suggestions as to how to make the commit message friendlier for reviewing. Generally, for every patch, we want to explain the following: what we want, why we want it and how we want to go about getting it. We also would prefer to do it in english rather than in C, because for the latter we can just look at the code." [1] I apologize for quoting myself or if I'm stating the obvious, but it looks appropriate here. [1] https://marc.info/?l=linux-kernel&m=152233031020263 Regards, -- Alex
> > From: Chao Peng <chao.p.peng@linux.intel.com> > > > > Disable intercept Intel PT MSRs only when Intel PT is enabled in > > guest. But MSR_IA32_RTIT_CTL will alway be intercept. > > "I'd like to offer some suggestions as to how to make the commit message > friendlier for reviewing. > > Generally, for every patch, we want to explain the following: what we want, > why we want it and how we want to go about getting it. We also would > prefer to do it in english rather than in C, because for the latter we can just > look at the code." [1] > > I apologize for quoting myself or if I'm stating the obvious, but it looks > appropriate here. > > [1] https://marc.info/?l=linux-kernel&m=152233031020263 > Thank you very much. My English is not good and lack some experience of how to make description more clearly. Will improve it. Thanks, Luwei Kang
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 770cb7c..a09157c 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -948,6 +948,7 @@ static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type); +static void pt_set_intercept_for_msr(struct vcpu_vmx *vmx, bool flag); static DEFINE_PER_CPU(struct vmcs *, vmxarea); static DEFINE_PER_CPU(struct vmcs *, current_vmcs); @@ -3999,6 +4000,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) vmx_rtit_ctl_check(vcpu, data)) return 1; vmcs_write64(GUEST_IA32_RTIT_CTL, data); + pt_set_intercept_for_msr(vmx, !(data & RTIT_CTL_TRACEEN)); vmx->pt_desc.guest.ctl = data; break; case MSR_IA32_RTIT_STATUS: @@ -5820,6 +5822,27 @@ static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) vmx->msr_bitmap_mode = mode; } +static void pt_set_intercept_for_msr(struct vcpu_vmx *vmx, bool flag) +{ + unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; + u32 i; + + vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, + MSR_TYPE_RW, flag); + vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, + MSR_TYPE_RW, flag); + vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, + MSR_TYPE_RW, flag); + vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, + MSR_TYPE_RW, flag); + for (i = 0; i < vmx->pt_desc.addr_range; i++) { + vmx_set_intercept_for_msr(msr_bitmap, + MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); + vmx_set_intercept_for_msr(msr_bitmap, + MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); + } +} + static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) { return enable_apicv;