| Message ID | 1526964735-16566-4-git-send-email-luwei.kang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 22, 2018 at 12:52:06PM +0800, Luwei Kang wrote: > These bit definitions are use for emulate MSRs read/write > for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available > only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest > try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 > a #GP would be injected to KVM guest. Do we have anything in the guest that this feature will work with? Regards, -- Alex
> > These bit definitions are use for emulate MSRs read/write for KVM. For > > example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when > > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this > > bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected > > to KVM guest. > > Do we have anything in the guest that this feature will work with? > It depend on PT driver. KVM need to do some security check if kvm guest (maybe linux or other os) try to set any bits of these MSRs. Thanks, Luwei Kang
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index afe4e13..6ae2462 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -112,6 +112,7 @@ #define RTIT_CTL_USR BIT(3) #define RTIT_CTL_PWR_EVT_EN BIT(4) #define RTIT_CTL_FUP_ON_PTW BIT(5) +#define RTIT_CTL_FABRIC_EN BIT(6) #define RTIT_CTL_CR3EN BIT(7) #define RTIT_CTL_TOPA BIT(8) #define RTIT_CTL_MTC_EN BIT(9) @@ -140,6 +141,8 @@ #define RTIT_STATUS_BUFFOVF BIT(3) #define RTIT_STATUS_ERROR BIT(4) #define RTIT_STATUS_STOPPED BIT(5) +#define RTIT_STATUS_BYTECNT_OFFSET 32 +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
These bit definitions are use for emulate MSRs read/write for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected to KVM guest. Signed-off-by: Luwei Kang <luwei.kang@intel.com> --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+)