From patchwork Wed May 23 07:01:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: simon X-Patchwork-Id: 10420503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 019EC6016C for ; Wed, 23 May 2018 07:47:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E940228F1D for ; Wed, 23 May 2018 07:47:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E798F28F47; Wed, 23 May 2018 07:47:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EA2628F47 for ; Wed, 23 May 2018 07:47:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932066AbeEWHrt (ORCPT ); Wed, 23 May 2018 03:47:49 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:35003 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754450AbeEWHrl (ORCPT ); Wed, 23 May 2018 03:47:41 -0400 Received: by mail-pg0-f67.google.com with SMTP id 11-v6so7405593pge.2; Wed, 23 May 2018 00:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zC+GkzWjKiAfEYbZyp074tbMOg41YKBGa+NyowQxZqw=; b=kwuA4PFQRps8k1qA4IIMzWltBuX82UwAX6c9JjQRBAsHfWyQ4O0NV+x0D9RbodwEfC /q7akFQvPSS1LL0RhB6roL0evOtYteNPvf3R39u7UaRKD2Bdi4KEIx1kJzfhJkkX8IGS cqCbgeEOPTpbnhV/hCZicm/+q2jEWoXUAyM28pK+zLVXjvJrji5zbnCozAXD6zL5xqqp L+OcGBi29nI/4zDctP5AHWdfo5W2X4iPA/o9+A4LXYpat+XoSHT1H2Sw3VO38F4pSdwo xc5uY2ReLwkoGAEuUHYjqttuKrwbsJktNgit3kuzXsUerkjhGACJ1GmmeNPnwI1jfQSn A/6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zC+GkzWjKiAfEYbZyp074tbMOg41YKBGa+NyowQxZqw=; b=fAD+NIQRe+G/5ANW9S/gOqcoziCuHpmEh6Sd2hnPzaG52PIfOTfNFiE2MPnYsmsP0i fZX6LlHQ6XQQAJrKF5v8kXtPDKTCAullOs4BDnBldMTQx0MrtHl/Yw8T3pbi4DyVu41+ /Ikg2QpSch0clExOz33GXkZ+3YWzjKs3vfLeZxLv8Bn6Nxp46eNCer1bT9FN7ugQVTu9 0V7bd32ft7zpckR7QhOWj/WN7fbSOXtNhAssXiHZanwA/Cjklngcsv5B512rbaU0y88C UwMehKRaLzadF+YYGIwzS4UG+ngp5q0ICkmDnjVDB3EDBSlpDR9CF7rqDKvh7no34Qil EF6Q== X-Gm-Message-State: ALKqPwf5oB8kgpfrLsg6bswuHphWHvXIXjekHkM1yfrJNxJx1oFCL8G1 4vlhowrcKaubZ0MIKlP2qAw= X-Google-Smtp-Source: AB8JxZpahInwcRh2RAGIogY7lxDdp7skhO1+9sRm+5QaCAOzVhw9c+QIE8PkZ7B29C//0+2s2WzQqw== X-Received: by 2002:a63:2647:: with SMTP id m68-v6mr1474767pgm.56.1527061660558; Wed, 23 May 2018 00:47:40 -0700 (PDT) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.89]) by smtp.gmail.com with ESMTPSA id a4-v6sm39079171pfj.19.2018.05.23.00.47.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 May 2018 00:47:39 -0700 (PDT) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH v4 10/29] KVM: PPC: Book3S PR: Sync TM bits to shadow msr for problem state guest Date: Wed, 23 May 2018 15:01:53 +0800 Message-Id: <1527058932-7434-11-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> References: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Simon Guo MSR TS bits can be modified with non-privileged instruction like tbegin./tend. That means guest can change MSR value "silently" without notifying host. It is necessary to sync the TM bits to host so that host can calculate shadow msr correctly. note privilege guest will always fail transactions so we only take care of problem state guest. The logic is put into kvmppc_copy_from_svcpu() so that kvmppc_handle_exit_pr() can use correct MSR TM bits even when preemption. Signed-off-by: Simon Guo --- arch/powerpc/kvm/book3s_pr.c | 73 ++++++++++++++++++++++++++++++-------------- 1 file changed, 50 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index d3237f5..f2ae5a3 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -182,10 +182,36 @@ void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu) svcpu_put(svcpu); } +static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) +{ + ulong guest_msr = kvmppc_get_msr(vcpu); + ulong smsr = guest_msr; + + /* Guest MSR values */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | + MSR_TM | MSR_TS_MASK; +#else + smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; +#endif + /* Process MSR values */ + smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; + /* External providers the guest reserved */ + smsr |= (guest_msr & vcpu->arch.guest_owned_ext); + /* 64-bit Process MSR values */ +#ifdef CONFIG_PPC_BOOK3S_64 + smsr |= MSR_ISF | MSR_HV; +#endif + vcpu->arch.shadow_msr = smsr; +} + /* Copy data touched by real-mode code from shadow vcpu back to vcpu */ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) { struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + ulong old_msr; +#endif /* * Maybe we were already preempted and synced the svcpu from @@ -228,6 +254,30 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb; if (cpu_has_feature(CPU_FTR_ARCH_207S)) vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic; + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * Unlike other MSR bits, MSR[TS]bits can be changed at guest without + * notifying host: + * modified by unprivileged instructions like "tbegin"/"tend"/ + * "tresume"/"tsuspend" in PR KVM guest. + * + * It is necessary to sync here to calculate a correct shadow_msr. + * + * privileged guest's tbegin will be failed at present. So we + * only take care of problem state guest. + */ + old_msr = kvmppc_get_msr(vcpu); + if (unlikely((old_msr & MSR_PR) && + (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != + (old_msr & (MSR_TS_MASK)))) { + old_msr &= ~(MSR_TS_MASK); + old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); + kvmppc_set_msr_fast(vcpu, old_msr); + kvmppc_recalc_shadow_msr(vcpu); + } +#endif + svcpu->in_use = false; out: @@ -306,29 +356,6 @@ static void kvm_set_spte_hva_pr(struct kvm *kvm, unsigned long hva, pte_t pte) /*****************************************/ -static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) -{ - ulong guest_msr = kvmppc_get_msr(vcpu); - ulong smsr = guest_msr; - - /* Guest MSR values */ -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | - MSR_TM | MSR_TS_MASK; -#else - smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; -#endif - /* Process MSR values */ - smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; - /* External providers the guest reserved */ - smsr |= (guest_msr & vcpu->arch.guest_owned_ext); - /* 64-bit Process MSR values */ -#ifdef CONFIG_PPC_BOOK3S_64 - smsr |= MSR_ISF | MSR_HV; -#endif - vcpu->arch.shadow_msr = smsr; -} - static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) { ulong old_msr = kvmppc_get_msr(vcpu);