From patchwork Wed May 23 07:02:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: simon X-Patchwork-Id: 10420523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3EA9A6016C for ; Wed, 23 May 2018 07:48:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 312F228DBA for ; Wed, 23 May 2018 07:48:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2605B28EA8; Wed, 23 May 2018 07:48:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D796228DBA for ; Wed, 23 May 2018 07:48:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754519AbeEWHsk (ORCPT ); Wed, 23 May 2018 03:48:40 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:46007 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932125AbeEWHsD (ORCPT ); Wed, 23 May 2018 03:48:03 -0400 Received: by mail-pl0-f67.google.com with SMTP id bi12-v6so12492341plb.12; Wed, 23 May 2018 00:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6ACv+jmr95fsRYlHoimgbUkMGRfAvdXlIQIZ6TPsBgY=; b=p8D2oRWr/xcen2dmbZpCcfW/EeI08LkgK683G8EPoKq2Oqe5+Dvh9rN305iEiBF31X 1wnGKus8akTFjgA2/WVsZ5bZXkwYAC9h9U8ArEoL0cc9CP6KHZ+ppQiBCgcjcI8a/ebX ASDcEdYD4phS7bTADcjmdoyS3v3CIP+W15CPT+VR0w/vHKwWBHctN5lOenbjQpt39nLP OBDEGL/D4Nq/7Rrko0sK0WxEo78hnbGMNkQlzeYrG5mbp4MCeqYqd6kneZR4abiQ2e1L Gtijq7NK3gVheq9RIc/PWAuADzpTOHm1Osg7nHAJAVqsggBrOJg2PdQP1C3yAvU+TYCc rHtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6ACv+jmr95fsRYlHoimgbUkMGRfAvdXlIQIZ6TPsBgY=; b=XTFRUTVJurgwMSfojfxVGNhFKdj1gZ/Vn1LkIkYaOgosiPl7QFwNmaSJ1BKXe68a1S I9zLm7wHuQS7iWsRwCAbYDjFrVNjM6x/n/8/JQWVUTFY+TdhOPXFaReFpGbfX+eajnZj AxDXEukJJSjbsW3ACIBoN86XC3V9+1UI0+8yxkbO+VtjT8q9XMdQ4zApPlEpr+JOnK2r VCE1HzKJINkWdIH8tmHYKZOgb4fJdYEiRtALmek6dB+anai1uCQhNGIZ0dwKT2WAeVQG 6mrbJ4OKYnIAjlJPqP9Twcqihr8mM62MkyZd7CTHfwszdHNh34P0o20lEmryg2Ri/2XX bTWQ== X-Gm-Message-State: ALKqPweWpJPNQPV9OswFXwuuQt0z8krnoMLtbHbqWBuSuAzodDyUZb2Z QbxHlvOaFXZibIBE81GhYnY= X-Google-Smtp-Source: AB8JxZoxnTm/wBZsQH+GE6rG+UuhO50V6iz/JlGYhFXdhfjw5OTxfCvthesFACOoASGvp6FaNavJNw== X-Received: by 2002:a17:902:43a4:: with SMTP id j33-v6mr1913715pld.118.1527061682536; Wed, 23 May 2018 00:48:02 -0700 (PDT) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.89]) by smtp.gmail.com with ESMTPSA id a4-v6sm39079171pfj.19.2018.05.23.00.48.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 May 2018 00:48:02 -0700 (PDT) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH v4 18/29] KVM: PPC: Book3S PR: always fail transaction in guest privilege state Date: Wed, 23 May 2018 15:02:01 +0800 Message-Id: <1527058932-7434-19-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> References: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Simon Guo Currently kernel doesn't use transaction memory. And there is an issue for privilege guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trap into PR host. So following code will lead to a false mfmsr result: tbegin <- MSR bits update to Transaction active. beq <- failover handler branch mfmsr <- still read MSR bits from magic page with transaction inactive. It is not an issue for non-privilege guest since its mfmsr is not patched with magic page and will always trap into PR host. This patch will always fail tbegin attempt for privilege guest, so that the above issue is prevented. It is benign since currently (guest) kernel doesn't initiate a transaction. Test case: https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.c Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_book3s.h | 2 ++ arch/powerpc/kvm/book3s_emulate.c | 40 +++++++++++++++++++++++++++++++++++ arch/powerpc/kvm/book3s_pr.c | 11 +++++++++- 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 43e8bb1..c1cea82 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -262,9 +262,11 @@ extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr, #ifdef CONFIG_PPC_TRANSACTIONAL_MEM void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); +void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu); #else static inline void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) {} static inline void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) {} +static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) {} #endif extern int kvm_irq_bypass; diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index c4e3ec6..570339b 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "book3s.h" #include @@ -48,6 +49,8 @@ #define OP_31_XOP_EIOIO 854 #define OP_31_XOP_SLBMFEE 915 +#define OP_31_XOP_TBEGIN 654 + /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 @@ -363,6 +366,43 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, break; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + case OP_31_XOP_TBEGIN: + { + if (!cpu_has_feature(CPU_FTR_TM)) + break; + + if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { + kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); + emulated = EMULATE_AGAIN; + break; + } + + if (!(kvmppc_get_msr(vcpu) & MSR_PR)) { + preempt_disable(); + vcpu->arch.cr = (CR0_TBEGIN_FAILURE | + (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT))); + + vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT | + (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) + << TEXASR_FC_LG)); + + if ((inst >> 21) & 0x1) + vcpu->arch.texasr |= TEXASR_ROT; + + if (kvmppc_get_msr(vcpu) & MSR_HV) + vcpu->arch.texasr |= TEXASR_HV; + + vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4; + vcpu->arch.tfiar = kvmppc_get_pc(vcpu); + + kvmppc_restore_tm_sprs(vcpu); + preempt_enable(); + } else + emulated = EMULATE_FAIL; + break; + } +#endif default: emulated = EMULATE_FAIL; } diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index e8e7f3a..9becca1 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -207,6 +207,15 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) #ifdef CONFIG_PPC_BOOK3S_64 smsr |= MSR_ISF | MSR_HV; #endif +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * in guest privileged state, we want to fail all TM transactions. + * So disable MSR TM bit so that all tbegin. will be able to be + * trapped into host. + */ + if (!(guest_msr & MSR_PR)) + smsr &= ~MSR_TM; +#endif vcpu->arch.shadow_msr = smsr; } @@ -299,7 +308,7 @@ static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } -static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) +void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) { tm_enable(); mtspr(SPRN_TFHAR, vcpu->arch.tfhar);