| Message ID | 1532598182-10711-5-git-send-email-luwei.kang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Intel Processor Trace virtualization enabling | expand |
Luwei Kang <luwei.kang@intel.com> writes: > These bit definitions are use for emulate MSRs read/write > for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available > only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest > try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 > a #GP would be injected to KVM guest. Please refrain from listing bit definitions in the patch description. We can see them from the patch diff, that is enough for the reviewer. Patch description has to explain what is happening and why. For example, "KVM needs these bit definitions to moderate guest access to corresponding features, based on the availablility of these features as advertised via CPUID". Or, "KVM will use these bit definitions to prevent the guest from using them when corresponding features are not available". Whichever is easier to formulate. > > Signed-off-by: Luwei Kang <luwei.kang@intel.com> > --- > arch/x86/include/asm/msr-index.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 5d560aa..7ad1e41 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -119,6 +119,7 @@ > #define RTIT_CTL_USR BIT(3) > #define RTIT_CTL_PWR_EVT_EN BIT(4) > #define RTIT_CTL_FUP_ON_PTW BIT(5) > +#define RTIT_CTL_FABRIC_EN BIT(6) > #define RTIT_CTL_CR3EN BIT(7) > #define RTIT_CTL_TOPA BIT(8) > #define RTIT_CTL_MTC_EN BIT(9) > @@ -147,6 +148,8 @@ > #define RTIT_STATUS_BUFFOVF BIT(3) > #define RTIT_STATUS_ERROR BIT(4) > #define RTIT_STATUS_STOPPED BIT(5) > +#define RTIT_STATUS_BYTECNT_OFFSET 32 > +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) The ByteCnt doesn't throw #GP, does it? Should it be in this patch? Thanks, -- Alex
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 5d560aa..7ad1e41 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -119,6 +119,7 @@ #define RTIT_CTL_USR BIT(3) #define RTIT_CTL_PWR_EVT_EN BIT(4) #define RTIT_CTL_FUP_ON_PTW BIT(5) +#define RTIT_CTL_FABRIC_EN BIT(6) #define RTIT_CTL_CR3EN BIT(7) #define RTIT_CTL_TOPA BIT(8) #define RTIT_CTL_MTC_EN BIT(9) @@ -147,6 +148,8 @@ #define RTIT_STATUS_BUFFOVF BIT(3) #define RTIT_STATUS_ERROR BIT(4) #define RTIT_STATUS_STOPPED BIT(5) +#define RTIT_STATUS_BYTECNT_OFFSET 32 +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
These bit definitions are use for emulate MSRs read/write for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected to KVM guest. Signed-off-by: Luwei Kang <luwei.kang@intel.com> --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+)