| Message ID | 1555536851-17462-15-git-send-email-fenghua.yu@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/split_lock: Enable split lock detection | expand |
On Wed, 17 Apr 2019, Fenghua Yu wrote: > A split locked access locks bus and degrades overall memory access > performance. When split lock detection feature is enumerated, enable > the feature by default to find any split lock issue. > > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> > --- > arch/x86/kernel/cpu/intel.c | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c > index 997d683d3c27..6a692d215bef 100644 > --- a/arch/x86/kernel/cpu/intel.c > +++ b/arch/x86/kernel/cpu/intel.c > @@ -34,6 +34,8 @@ > DEFINE_PER_CPU(u64, msr_test_ctl_cache); > EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache); > > +static bool split_lock_detect_enable; > + > /* > * Just in case our CPU detection goes bad, or you have a weird system, > * allow a way to override the automatic disabling of MPX. > @@ -164,6 +166,23 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c) > return false; > } > > +static void split_lock_update_msr(void *__unused) > +{ > + if (split_lock_detect_enable) { > + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); > + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT); > + } else { > + msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); > + this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT); > + } Nothing in this file initializes msr_test_ctl_cache explicitely. Register caching always requires to read the register and store it in the cache before doing anything with it. Nothing guarantees that all bits in that MSR are 0 by default forever. And once you do that _before_ calling split_lock_update_msr() then you can spare the RMW in that function. > +static void init_split_lock_detect(struct cpuinfo_x86 *c) > +{ > + if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT)) > + split_lock_update_msr(NULL); > +} > + > static void early_init_intel(struct cpuinfo_x86 *c) > { > u64 misc_enable; > @@ -661,6 +680,8 @@ static void init_intel(struct cpuinfo_x86 *c) > { > early_init_intel(c); > > + init_split_lock_detect(c); Sigh. Why needs this to be squeezed in the middle of the whole enumeration stuff? Just because.... init_intel_misc_features() is called at the end and it does also MSR caching etc. So down there is the right place. > + > intel_workarounds(c); > > /* > @@ -1032,9 +1053,22 @@ static const struct cpu_dev intel_cpu_dev = { > > cpu_dev_register(intel_cpu_dev); > > +#undef pr_fmt > +#define pr_fmt(fmt) "x86/split lock detection: " fmt > + > +static void show_split_lock_detection_info(void) > +{ > + if (split_lock_detect_enable) > + pr_info("enabled\n"); > + else > + pr_info("disabled\n"); This function is truly useful. The else path is never invoked. See the call site below. > +} > + > static void __init set_split_lock_detect(void) > { > setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); > + split_lock_detect_enable = true; > + show_split_lock_detection_info(); > } Oh well. Thanks, tglx
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 997d683d3c27..6a692d215bef 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -34,6 +34,8 @@ DEFINE_PER_CPU(u64, msr_test_ctl_cache); EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache); +static bool split_lock_detect_enable; + /* * Just in case our CPU detection goes bad, or you have a weird system, * allow a way to override the automatic disabling of MPX. @@ -164,6 +166,23 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c) return false; } +static void split_lock_update_msr(void *__unused) +{ + if (split_lock_detect_enable) { + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT); + } else { + msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT); + } +} + +static void init_split_lock_detect(struct cpuinfo_x86 *c) +{ + if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT)) + split_lock_update_msr(NULL); +} + static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; @@ -661,6 +680,8 @@ static void init_intel(struct cpuinfo_x86 *c) { early_init_intel(c); + init_split_lock_detect(c); + intel_workarounds(c); /* @@ -1032,9 +1053,22 @@ static const struct cpu_dev intel_cpu_dev = { cpu_dev_register(intel_cpu_dev); +#undef pr_fmt +#define pr_fmt(fmt) "x86/split lock detection: " fmt + +static void show_split_lock_detection_info(void) +{ + if (split_lock_detect_enable) + pr_info("enabled\n"); + else + pr_info("disabled\n"); +} + static void __init set_split_lock_detect(void) { setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); + split_lock_detect_enable = true; + show_split_lock_detection_info(); } void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
A split locked access locks bus and degrades overall memory access performance. When split lock detection feature is enumerated, enable the feature by default to find any split lock issue. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> --- arch/x86/kernel/cpu/intel.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)