@@ -70,6 +70,8 @@ static void vtd_pasid_cache_reset(IntelIOMMUState *s);
static int vtd_pasid_cache_psi(IntelIOMMUState *s,
uint16_t domain_id,
uint32_t pasid);
+static void vtd_pasid_cache_devsi(IntelIOMMUState *s,
+ uint16_t devfn);
static VTDContextCacheEntry *vtd_find_context_cache(IntelIOMMUState *s,
PCIBus *bus, int devfn);
static void vtd_invalidate_pe_cache(IntelIOMMUState *s,
@@ -1955,6 +1957,7 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
* check if the device has been bound to any pasid
* invoke pasid_unbind regards to each bound pasid
*/
+ vtd_pasid_cache_devsi(s, devfn_it);
}
}
}
@@ -3686,6 +3689,11 @@ static inline bool vtd_pc_is_pasid_si(struct VTDPASIDCacheInfo *pc_info)
return pc_info->flags & VTD_PASID_CACHE_PASIDSI;
}
+static inline bool vtd_pc_is_dev_si(struct VTDPASIDCacheInfo *pc_info)
+{
+ return pc_info->flags & VTD_PASID_CACHE_DEVSI;
+}
+
/**
* This function is used to clear pasid_cache_gen of cached pasid
* entry in vtd_pasid_as instance. Caller of this function should
@@ -3709,6 +3717,7 @@ static gboolean vtd_flush_pasid(gpointer key, gpointer value,
pasid = vtd_pasid_as->pasid;
devfn = vtd_pasid_as->devfn;
if (vtd_pasid_as->pasid_cache_entry.pasid_cache_gen &&
+ (vtd_pc_is_dev_si(pc_info) ? (pc_info->devfn == devfn) : 1) &&
(vtd_pc_is_dom_si(pc_info) ? (pc_info->domain_id == did) : 1) &&
(vtd_pc_is_pasid_si(pc_info) ? (pc_info->pasid == pasid) : 1)) {
/*
@@ -3917,6 +3926,19 @@ static int vtd_pasid_cache_psi(IntelIOMMUState *s,
return 0;
}
+static void vtd_pasid_cache_devsi(IntelIOMMUState *s,
+ uint16_t devfn)
+{
+ VTDPASIDCacheInfo pc_info;
+
+ trace_vtd_pasid_cache_devsi(devfn);
+
+ pc_info.flags = VTD_PASID_CACHE_DEVSI;
+ pc_info.devfn = devfn;
+
+ g_hash_table_foreach_remove(s->vtd_pasid_as, vtd_flush_pasid, &pc_info);
+}
+
/**
* Caller of this function should hold iommu_lock
*/
@@ -485,9 +485,11 @@ typedef enum VTDPASIDOp VTDPASIDOp;
struct VTDPASIDCacheInfo {
#define VTD_PASID_CACHE_DOMSI (1ULL << 0);
#define VTD_PASID_CACHE_PASIDSI (1ULL << 1);
+#define VTD_PASID_CACHE_DEVSI (1ULL << 2);
uint32_t flags;
uint16_t domain_id;
uint32_t pasid;
+ uint16_t devfn;
};
typedef struct VTDPASIDCacheInfo VTDPASIDCacheInfo;
@@ -26,6 +26,7 @@ vtd_pasid_cache_reset(void) ""
vtd_pasid_cache_gsi(void) ""
vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation domain 0x%"PRIx16
vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32
+vtd_pasid_cache_devsi(uint16_t devfn) "Dev slective PC invalidation dev: 0x%"PRIx16
vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"
vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present"
vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16
This patch flushes pasid cache after a device selective context cache flush. This is a behavior to ensure safety. Actually, programmer should issue a pasid cache flush following a device selective context cache invalidation. TODO: global and domain selective context cache flush should also be followed with a proper pasid cache flush. Also needs to consider pasid bind replay. Cc: Kevin Tian <kevin.tian@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Peter Xu <peterx@redhat.com> Cc: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> --- hw/i386/intel_iommu.c | 22 ++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/trace-events | 1 + 3 files changed, 25 insertions(+)