From patchwork Sat Sep 7 00:13:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Rosato X-Patchwork-Id: 11136159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBF16112B for ; Sat, 7 Sep 2019 00:14:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF1872178F for ; Sat, 7 Sep 2019 00:14:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406169AbfIGAOO (ORCPT ); Fri, 6 Sep 2019 20:14:14 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:29268 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393514AbfIGAOM (ORCPT ); Fri, 6 Sep 2019 20:14:12 -0400 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x8707Ngh113588; Fri, 6 Sep 2019 20:13:58 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 2uuwu0evgm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2019 20:13:58 -0400 Received: from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.27/8.16.0.27) with SMTP id x8707aUl115701; Fri, 6 Sep 2019 20:13:57 -0400 Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 2uuwu0evg9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2019 20:13:57 -0400 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id x8709N3j004282; Sat, 7 Sep 2019 00:13:56 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma02dal.us.ibm.com with ESMTP id 2uqgh8285u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 07 Sep 2019 00:13:56 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x870DroP47513980 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 7 Sep 2019 00:13:54 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC556124054; Sat, 7 Sep 2019 00:13:53 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55829124052; Sat, 7 Sep 2019 00:13:53 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.85.134.207]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Sat, 7 Sep 2019 00:13:53 +0000 (GMT) From: Matthew Rosato To: sebott@linux.ibm.com Cc: gerald.schaefer@de.ibm.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, walling@linux.ibm.com, linux-s390@vger.kernel.org, iommu@lists.linux-foundation.org, joro@8bytes.org, linux-kernel@vger.kernel.org, alex.williamson@redhat.com, kvm@vger.kernel.org, heiko.carstens@de.ibm.com, robin.murphy@arm.com, gor@linux.ibm.com, cohuck@redhat.com, pmorel@linux.ibm.com Subject: [PATCH v4 1/4] s390: pci: Exporting access to CLP PCI function and PCI group Date: Fri, 6 Sep 2019 20:13:48 -0400 Message-Id: <1567815231-17940-2-git-send-email-mjrosato@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1567815231-17940-1-git-send-email-mjrosato@linux.ibm.com> References: <1567815231-17940-1-git-send-email-mjrosato@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-09-06_11:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1909070000 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Pierre Morel For the generic implementation of VFIO PCI we need to retrieve the hardware configuration for the PCI functions and the PCI function groups. We modify the internal function using CLP Query PCI function and CLP query PCI function group so that they can be called from outside the S390 architecture PCI code and prefix the two functions with "zdev" to make clear that they can be called knowing only the associated zdevice. Signed-off-by: Pierre Morel Reviewed-by: Sebastian Ott --- arch/s390/include/asm/pci.h | 3 ++ arch/s390/pci/pci_clp.c | 71 +++++++++++++++++++++++---------------------- 2 files changed, 40 insertions(+), 34 deletions(-) diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index a2399ef..dd03212 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -266,4 +266,7 @@ static inline int __pcibus_to_node(const struct pci_bus *bus) #endif /* CONFIG_NUMA */ +int zdev_query_pci_fngrp(struct zpci_dev *zdev, + struct clp_req_rsp_query_pci_grp *rrb); +int zdev_query_pci_fn(struct zpci_dev *zdev, struct clp_req_rsp_query_pci *rrb); #endif diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c index 9bdff4d..df06fdf 100644 --- a/arch/s390/pci/pci_clp.c +++ b/arch/s390/pci/pci_clp.c @@ -113,32 +113,18 @@ static void clp_store_query_pci_fngrp(struct zpci_dev *zdev, } } -static int clp_query_pci_fngrp(struct zpci_dev *zdev, u8 pfgid) +int zdev_query_pci_fngrp(struct zpci_dev *zdev, + struct clp_req_rsp_query_pci_grp *rrb) { - struct clp_req_rsp_query_pci_grp *rrb; - int rc; - - rrb = clp_alloc_block(GFP_KERNEL); - if (!rrb) - return -ENOMEM; - memset(rrb, 0, sizeof(*rrb)); rrb->request.hdr.len = sizeof(rrb->request); rrb->request.hdr.cmd = CLP_QUERY_PCI_FNGRP; rrb->response.hdr.len = sizeof(rrb->response); - rrb->request.pfgid = pfgid; + rrb->request.pfgid = zdev->pfgid; - rc = clp_req(rrb, CLP_LPS_PCI); - if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) - clp_store_query_pci_fngrp(zdev, &rrb->response); - else { - zpci_err("Q PCI FGRP:\n"); - zpci_err_clp(rrb->response.hdr.rsp, rc); - rc = -EIO; - } - clp_free_block(rrb); - return rc; + return clp_req(rrb, CLP_LPS_PCI); } +EXPORT_SYMBOL(zdev_query_pci_fngrp); static int clp_store_query_pci_fn(struct zpci_dev *zdev, struct clp_rsp_query_pci *response) @@ -174,32 +160,49 @@ static int clp_store_query_pci_fn(struct zpci_dev *zdev, return 0; } -static int clp_query_pci_fn(struct zpci_dev *zdev, u32 fh) +int zdev_query_pci_fn(struct zpci_dev *zdev, struct clp_req_rsp_query_pci *rrb) +{ + + memset(rrb, 0, sizeof(*rrb)); + rrb->request.hdr.len = sizeof(rrb->request); + rrb->request.hdr.cmd = CLP_QUERY_PCI_FN; + rrb->response.hdr.len = sizeof(rrb->response); + rrb->request.fh = zdev->fh; + + return clp_req(rrb, CLP_LPS_PCI); +} + +static int clp_query_pci(struct zpci_dev *zdev) { struct clp_req_rsp_query_pci *rrb; + struct clp_req_rsp_query_pci_grp *grrb; int rc; rrb = clp_alloc_block(GFP_KERNEL); if (!rrb) return -ENOMEM; - memset(rrb, 0, sizeof(*rrb)); - rrb->request.hdr.len = sizeof(rrb->request); - rrb->request.hdr.cmd = CLP_QUERY_PCI_FN; - rrb->response.hdr.len = sizeof(rrb->response); - rrb->request.fh = fh; - - rc = clp_req(rrb, CLP_LPS_PCI); - if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) { - rc = clp_store_query_pci_fn(zdev, &rrb->response); - if (rc) - goto out; - rc = clp_query_pci_fngrp(zdev, rrb->response.pfgid); - } else { + rc = zdev_query_pci_fn(zdev, rrb); + if (rc || rrb->response.hdr.rsp != CLP_RC_OK) { zpci_err("Q PCI FN:\n"); zpci_err_clp(rrb->response.hdr.rsp, rc); rc = -EIO; + goto out; } + rc = clp_store_query_pci_fn(zdev, &rrb->response); + if (rc) + goto out; + + grrb = (struct clp_req_rsp_query_pci_grp *)rrb; + rc = zdev_query_pci_fngrp(zdev, grrb); + if (rc || grrb->response.hdr.rsp != CLP_RC_OK) { + zpci_err("Q PCI FGRP:\n"); + zpci_err_clp(grrb->response.hdr.rsp, rc); + rc = -EIO; + goto out; + } + clp_store_query_pci_fngrp(zdev, &grrb->response); + out: clp_free_block(rrb); return rc; @@ -219,7 +222,7 @@ int clp_add_pci_device(u32 fid, u32 fh, int configured) zdev->fid = fid; /* Query function properties and update zdev */ - rc = clp_query_pci_fn(zdev, fh); + rc = clp_query_pci(zdev); if (rc) goto error;